Digital Signal Processing 101

Michael Parker is responsible for Intel’s FPGA division digital signal processing (DSP) product planning. This includes Variable Precision FPGA silicon architecture for DSP applications, DSP tool development, floating point tools, IP and video IP. He joined Altera (now Intel) in January 2007, and has over 20 years of previous DSP engineering design experience with companies such as Alvarion, Soma Networks, Avalcom, TCSI, Stanford Telecom and several startup companies. He holds an MSEE from Santa Clara University, and BSEE from Rensselaer Polytechnic Institute.

1. Numerical Representation2. Complex Numbers and Exponentials3. Sampling, Aliasing and Quantization4. Frequency Response5. Finite Impulse Response (FIR) Filters6. Windowing7. Decimation and Interpolation8. Infinite Impulse Response (IIR) Filters9. Matrix Inversion algorithms (QR and Cholesky Decomposition)10. Complex Modulation and Demodulation11. Discrete and Fast Fourier Transforms (DFT, FFT)12. Discrete Cosine Transform (DCT)13. Digital Up and Down Conversion14. Error Correction Coding15. Analog and TDMA Wireless Communications16. CDMA Wireless Communications17. OFDMA Wireless Communications18. Radar Basics19. Pulse Doppler Radar20. FMCW Radar Signal Processing21. Space-Time Adaptive Processing Radar (STAP)22. Synthetic Array Radar (SAR)23. Field Orientated Motor Control24. Introduction to Video Processing25. Introduction to Video Compression26. Introduction to Machine Learning27. Implementation using Digital Signal Processors28. Implementation using FPGAs

Appendix A – Q Format Shift with Fractional MultiplicationAppendix B – Evaluation of FIR Design Error MinimizationAppendix C – Laplace transformAppendix D – Z transformAppendix E – Binary Field Arithmetic