Charge-Trapping Non-Volatile Memories (eBook)

Dr Panagiotis Dimitrakis graduated the Physics Department of the University of Athens (BSc 1995, MSc 1998) and received his PhD degree in the field of nanocrystal memories in 2006 from the School of Applied Mathematical and Physical Sciences of the National Technical University of Athens (NTUA). He has been employed by University of Athens, NTUA and National Research Center for Scientific Research “Demokritos” (NCSRD) in several Greek and competitive EU research projects as research scientist. In addition, he was principal investigator for NCSRD in a project funded by European Space Agency (ESA) on tunable photo-detector based on QDs. Currently, he is coordinating a project on resistive memories using graphene. He has published 50 papers in international peer-reviewed journals. He has 10 invited talks and more than 40 papers in international conference proceeding volumes on the physics and the electrical characterization of submicron MOSFETs, novel FET nano-devices, nonvolaitle memories, and organic electronic devices. Also he has published two book chapters in the field of nanoelectronic memories. More specifically, he has co-organized the NVM symposia in MRS Meetings from 2010 up to 2014. He is a Member of IEEE (Electron Devices Society) and Material Research Society (MRS) and reviewer in several international journals. He has participated in the technical program committees and has organized several international conferences and Workshops in Europe and USA and edited their proceedings. Presently, he is with Institute of Nanoscience & Nanotechnology (INN)-NCSRD (since 2007) where he is the manager of the Central Cleanroom Facility-Nanotechnology & Microsystems Laboratory. His research interests are focused in the field of nonvolatile memory devices, hybrid organic/inorganic semiconductor nano-devices, Graphene nanoelectronic devices as well as the physics and characterization of nanowire transistors and novel nanostructured photovoltaic devices.

Preface 6
Contents 8
About the Editor 10
Chapter 1: Introduction to NVM Devices 11
1.1 Basic Concepts and Devices for Nonvolatile Memories 14
1.1.1 FG Flash Cells 14
1.1.2 Quantum Dots (or Nanoparticle) NVM Flash Cells 30
1.1.3 CT Flash Cells 35
1.2 Perspectives 39
References 43
Chapter 2: A Synopsis on the State of the Art of NAND Memories 47
2.1 Introduction 47
2.2 A Short History of Nonvolatile Memories and NAND 48
2.3 Capacitive Coupling 48
2.3.1 Basic Coupling 50
2.4 Running Out of Electrons 51
2.5 Parasitic Capacitance 53
2.6 General NAND Scaling Issues 56
2.7 Failure of Charge Trapping Flash (CTF) Memories in NAND 57
2.8 Development of a Planar NAND Cell 58
2.9 Blocking Dielectric and Metal Gate Options 61
2.10 Silicon Nitride Based Charge Trap Flash (SN-CTF) 61
2.11 Metal Nanodot (NC) Based CTF (NC-CTF) 63
2.12 Thin Conductive Floating Gate Planar Cell 66
2.13 Results of NAND Scaling Study 67
2.14 Future of High Density Charge Trap Memories 68
2.15 Emerging Memories 69
2.16 Synopsis of Emerging Memory Challenges 71
References 73
Chapter 3: Charge-Trap Memories with Ion Beam Modified ONO Stacks 75
3.1 Introduction 75
3.2 Silicon Nitride Based Memory Structures 76
3.2.1 Early Work: The MNOS Memory Cell 76
3.2.2 The SONOS/MONOS Memory Device 78
3.2.3 Recent Developments of the Silicon Nitride Based Memory Cell 80
3.3 Formation of Silicon Nanoparticles Within the Nitride Layer 83
3.3.1 The Technique of Low-Energy Ion Beam Modification 83
3.3.2 Fabrication of Samples 84
3.3.3 Transmission Electron Microscopy 85
3.3.4 Current Density-Electric Field Characteristics 87
3.3.5 Capacitance-Voltage Characteristics 89
3.3.6 Memory Properties 90
3.3.7 Determination of the Trapping Location of Injected Charges 94
3.3.8 Performance and Retention 98
3.4 Wet Oxidation of Silicon Implanted Nitride Layers 100
3.4.1 Samples Fabrication 100
3.4.2 Structural Characterization 100
3.4.3 Charging Characteristics 105
3.4.4 Memory Properties 106
3.5 Prospects and Conclusions 109
References 110
Chapter 4: 3D NAND Flash Architectures 113
4.1 General Introduction 113
4.2 Brief Comparison of Various 3D NAND Flash and a General Cost Analysis 116
4.3 BiCS and P-BiCs 123
4.4 TCAD and VNAND 128
4.5 VG NAND 137
4.5.1 In-Layer Plural Normally on SSL Decoder (Kim et al. 2009b) 138
4.5.2 Island-Gate SSL Decoding Method (Lue et al. 2010 Chang et al. 2012)
4.5.3 Split-Page 3DVG Design (Chen et al. 2012a Hung et al. 2012
4.5.4 Self-Aligned Independent Double Gate (IDG) SSL Decoding Method (Chen et al. 2012b) 142
4.5.5 PN Diode Decoded 3DVG (Hung et al. 2011 Lue et al. 2013a)
4.5.6 Process Challenges of 3DVG 144
4.5.7 Device Performances of 3DVG 146
4.5.8 Integration Challenges 149
4.6 General Issues and Device Considerations in 3D NAND Flash 150
4.7 Innovative Device Operations or Structures for 3D NAND 157
4.7.1 Hot-Electron Assisted Programming Method for Reducing the Programming Voltages (Chang et al. 2013) 157
Source-Side Boosting 158
Drain-Side Boosting 158
P-Channel 3D NAND Flash (Lue et al. 2013b) 161
Dual-Channel 3D NAND Flash (Lue et al. 2013a) 165
4.8 Summary 169
References 170
Chapter 5: Quantum Dot Nonvolatile Memories 174
5.1 Introduction 174
5.2 Material and Size-Dependent Characteristics of QDs 178
5.3 Fabrication of QD-NVM Structures and Devices 184
5.3.1 Fabrication Techniques 184
5.3.2 Structures and Devices 185
5.4 Conclusion 187
References 188
Chapter 6: Two-Terminal Organic Memories with Metal or Semiconductor Nanoparticles 191
6.1 Introduction 191
6.2 Devices with a Metal Nanoparticle Layer Between Two Organic Layers 193
6.3 Devices with a Single Polymer Layer Embedded with Nanoparticles 197
6.4 Devices with Nanocomposites 200
6.5 Organic Memories Exploring the Contact Between Metal Nanoparticles and a Bulk Metal Electrode 202
6.6 Mechanisms for Resistive Switches 206
6.6.1 Electric-Field-Induced Charge Transfer Between Nanoparticles and Organic Semiconductor in the Active Layer 206
6.6.2 Charge Trapping on NPs 207
6.6.3 Electric Field-Induced Polarization 209
6.6.4 Resistive Switching Mechanism for the Devices Exploring the Interface Between Nanoparticles and Metal Electrodes 210
6.7 Memory Application 212
6.8 Conclusion and Outlook 215
References 216