Data Transmission at Millimeter Waves (eBook)

Acknowledgments 6
Contents 7
Figures 10
Tables 15
Abstract 16
1 Introduction 17
1.1 Motivation 17
1.2 60 GHz Area Background 18
1.2.1 Standards and Frequency Plan 18
1.2.2 Beamforming and System Architecture 19
1.2.3 Enabling Technology 21
1.2.4 Applications 22
1.3 Book Objectives 23
1.4 Organization of the Following Chapters 23
References 23
2 Background 25
2.1 QVCO 25
2.1.1 VCO Basics 25
2.1.2 Main Parameters 27
2.1.3 Phase Noise Origins 31
2.1.3.1 Resonator Noise 32
2.1.3.2 Differential Pair Noise 32
2.1.3.3 Tail Current Noise 32
2.1.4 Quadrature VCO 34
2.2 LO Buffer 36
2.3 Frequency Divider 40
2.3.1 ILFD 41
2.3.2 Static Divider 44
2.4 LNA 46
2.4.1 NF and IIP3 47
2.4.2 LNA Topology 49
2.5 Mixer 50
2.5.1 Main Parameters 51
2.5.2 Mixer Topology 52
References 54
3 Design and Simulation Results 56
3.1 fT of the 90 Nm NMOS Transistor 56
3.2 Passive Elements 57
3.2.1 Varactors 57
3.2.2 Transmission Lines 58
3.2.3 Inductors 59
3.2.4 Transformers 59
3.3 QVCO and LO Buffer 61
3.3.1 Circuit Schematic 61
3.3.2 Circuit Operation 63
3.3.2.1 External Gate Bias 63
3.3.2.2 Modal Determinism 63
3.3.2.3 Variable Coupling 66
3.3.2.4 Digital Varactor 66
3.3.2.5 Current Mirror 66
3.3.3 Design Guidelines 67
3.3.3.1 Cross-Coupled Pair 67
3.3.3.2 Digital Varactor 67
3.3.3.3 Differential Inductor 68
3.3.3.4 Quadrature Coupling 68
3.3.3.5 Current Mirror 69
3.3.3.6 Current Source 69
3.3.3.7 Output Voltage Swing 70
3.3.3.8 External Gate Bias 71
3.3.3.9 LO Buffer Transistor Size 71
3.3.3.10 LO Buffer Configuration 71
3.3.4 Design Values 72
3.3.5 Simulation Results of P-QVCO 72
3.3.5.1 Amplitude and Tuning Range 72
3.3.5.2 Phase Noise 72
3.3.5.3 Variations with Tail Current 74
3.3.5.4 Variations with Gate Voltage 75
3.3.5.5 Variations with Supply Voltage 76
3.3.5.6 Performance at a Reduced Load Size 77
3.3.6 Simulation Results of BS-QVCO 78
3.3.6.1 Performance at a Load Transistor of 40 mu m 78
3.3.6.2 Performance at a Load Transistor of 24 mu m 78
3.3.7 Performance Summary 78
3.4 Divider Chain 79
3.4.1 Circuit Schematic 80
3.4.2 ILFD Locking Range 80
3.4.3 Design Guidelines 83
3.4.3.1 First Analog Divider Stage 83
3.4.3.2 Second Analog Divider Stage 84
3.4.3.3 Static Dividers 84
3.4.4 Design Values 85
3.4.5 Simulation Results 85
3.4.5.1 60 GHz Divider 85
3.4.5.2 30 GHz Divider 85
3.4.5.3 First CML Divider 87
3.4.5.4 Second CML Divider 88
3.4.5.5 The Complete Divider Chain 88
3.4.6 Performance Summary 89
3.5 LNA and Mixer 90
3.5.1 Circuit Schematic 90
3.5.2 Design Guidelines 91
3.5.3 Design Values 91
3.5.4 Simulation Results 91
3.5.4.1 Conversion Gain 91
3.5.4.2 Noise Figure and S11 94
3.5.4.3 Linearity 94
3.5.4.4 Results at Reduced Power Consumption 95
3.5.5 Performance Summary 96
References 97
4 Top-Level Design 98
4.1 Complete Top-Level Circuit 98
4.1.1 Circuit Schematic 98
4.1.2 Design Choices 98
4.1.3 Design Values 100
4.1.4 Simulation Results 100
4.2 QVCO and Divider Sub-system 102
4.2.1 Circuit Schematic 102
4.2.2 Design Choices 102
4.2.3 Design Values 104
4.2.4 Simulation Results 104
4.2.4.1 Source Follower 104
4.2.4.2 Divider 106
4.2.4.3 QVCO and LO Buffer 107
Reference 108
5 Layout and Post-layout Simulations 109
5.1 Physical Layout 109
5.2 Nominal Simulation Result 109
5.2.1 Divider 111
5.2.2 QVCO and LO Buffer 112
5.3 PVT Simulations 114
6 Conclusions 116
6.1 Summary 116
6.2 Future Work 117
Reference 118
Transformer-Coupled Buffer 119