Routing Algorithms in Networks-on-Chip (eBook)

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2013 | 2014
XIV, 410 Seiten
Springer New York (Verlag)
978-1-4614-8274-1 (ISBN)

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This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation.  Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.
This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation. Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.

Part I Performance Improvement.- Basic Concepts on On-Chip Networks.- A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs.- Run-Time Deadlock Detection.- The Abacus Turn Model.- Learning-based Routing Algorithms for on-Chip Networks.- Part II Multicast Communication.- Efficient and Deadlock-Free Tree-based Multicast Routing Method for Network-on-Chip.- Path-based Multicast Routing for 2D and 3D Mesh Networks.- Part III Fault Tolerance and Reliability.- Fault-Tolerant Routing Algorithms in Networks-on-Chip.- Reliable and Adaptive Algorithms for 2D and 3D Networks-on-Chip.- Part IV Power/Energy and Thermal Issues.- Bufferless and Minimally-Buffered Deflection Routing.- A Thermal Aware Routing Algorithm for Application-Specific Network-on-Chip.- Part V Emerging Technologies.- Traffic- and Theme-Aware Routing Algorithms for 3D Network-on-Chip (3D NoC) Systems.- Scalable Architecture for All-Optical Wavelength-Routed Networks-on-Chip.- Part VI Industrial Case Study.- On Chip Network Routing for tera-scale architectures.-

Erscheint lt. Verlag 22.10.2013
Zusatzinfo XIV, 410 p. 219 illus., 97 illus. in color.
Verlagsort New York
Sprache englisch
Themenwelt Mathematik / Informatik Informatik Theorie / Studium
Technik Elektrotechnik / Energietechnik
Technik Nachrichtentechnik
Schlagworte Adaptive Routing in Network on Chip • Network on Chip • Network on Chip Routing Architecture • On-Chip Communication Architecture • Routing Algorithms for Intel 80-Core Chip • Routing Algorithms for Manycore Chips • Routing Algorithms for Network on Chip • Routing Algorithms for NXP Athereal • Routing Algorithms for ST Spidergon • Routing Algorithms for TILERA 100-Core Chi • Routing Algorithms for TILERA 100-Core Chip
ISBN-10 1-4614-8274-7 / 1461482747
ISBN-13 978-1-4614-8274-1 / 9781461482741
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