Inside Solid State Drives (SSDs) (eBook)

Rino Micheloni (rino.micheloni@ieee.org) is Lead Flash Technologist at IDT (Integrated Device Technology). He has 18 years experience in NAND/NOR Flash memory design, architecture and algorithms as well as the related intellectual property. Before IDT, he was Senior Principal for Flash and Director of Qimonda's design center in Italy, developing 36 nm and 48 nm NAND memories. From 2001 to 2006 he managed the Napoli design center of STMicroelectronics focusing on the development of 90 nm and 60 nm MLC NAND Flash. Before that, he led the development of MLC NOR Flash. He is co-author of 103 U.S. patents and five Springer books on NOR/NAND/ECC/SSD. He is IEEE Senior Member and received the STMicroelectronics Exceptional Patent in 2003 and 2004, and the Qimonda IP Award in 2007.  Alessia Marelli was born in Bergamo, Italy in 1980. She received her degree in Mathematical Science from “Università degli Studi di Milano – Bicocca”, Italy in 2003 with a thesis about ECC applied to Flash Memories. In 2003 she joined STMicroelectronics, Agrate B., Italy. She was involved in digital design of Multilevel NAND Memories, especially redundancy, ECC and algorithms. In 2007, she joined Qimonda as senior digital designer. In 2009 she joined Integrated Device Technology (IDT) as senior digital designer, where she takes care of ECC applied to SSD. She is co-author of some patents regarding Redundancy and ECC applied to Flash Memories. She is co-author of Memories in Wireless Systems (Springer, 2008), Error Correction Codes for Non-Volatile Memories (Springer, 2008), Inside NAND Flash Memories (Springer, 2010). Kam Eshghi is Sr. Director of Marketing in Enterprise Computing Division of IDT. Kam leads IDT’s business strategy, marketing and business development for flash controllers and PCIe switches. Kam drove the creation of IDT’s PCIe Enterprise Flash Controller product line and established IDT as a leader in this market.Kam has more than 18 years of industry experience. Prior to joining IDT, Kam built product lines in server and networking markets at HP, Intel, Crosslayer Networks, and Synopsys.  During his time at Intel, Kam led a team to define strategy and product roadmaps for server chipsets.  Previous to that as Vice President of Marketing and Business Development at Crosslayer Networks, Kam defined a family of Ethernet-IP switch processors and led all customer engagements, ultimately leading to LSI’s acquisition.Kam holds a M.S. in Electrical Engineering & Computer Science from Massachusetts Institute of Technology, and a Master’s in Business Administration and B.S. in Electrical Engineering & Computer Science both from University of California at Berkeley.

Inside Solid State Drives(SSDs) 3
Foreword 7
Error Correcting Coding for Solid State Disk Data Storage 7
Preface 9
About the Editors 13
Acknowledgements 15
Contents 17
Chapter 1: SSD Market Overview 19
1.1 Computing Market and Applications 19
1.2 SSD Overview 20
1.2.1 What Is a Solid State Drive? 20
1.2.2 The Memory Hierarchy 20
1.2.3 SSD vs. HDD 22
1.3 Client PC Applications 23
1.4 Notebook PCs and Tablets 25
1.5 Desktop PCs 26
1.6 Client PC and Tablet SSD Forecast 27
1.7 Enterprise Computing Applications 27
1.7.1 Transaction Processing 30
1.7.2 Video Server 31
1.7.3 High Performance Computing 31
1.7.4 Internet/Network Server 31
1.7.5 Server-Attached vs. Storage-Attached SSDs 32
1.8 Enterprise SSD Forecast 32
1.8.1 PCIe SSD 33
1.8.2 SATA Boot Drives 34
1.8.3 SATA Drives 34
1.8.4 Fiber Channel/SAS 34
References 35
Chapter 2: SSD Architecture and PCI Express Interface 36
2.1 Introduction 36
2.2 SSD Architecture 37
2.3 Non-volatile Memories 38
2.4 NAND Flash 39
2.4.1 NAND Array 39
2.4.2 NAND Interface 41
2.5 Memory Controller 43
2.5.1 Wear Leveling 45
2.5.2 Garbage Collection 46
2.5.3 Bad Block Management 47
2.5.4 Error Correction Code (ECC) 47
2.6 Multi-channel Architecture 48
2.7 What Is PCIe? 50
2.8 The Need for Storage Speed 54
2.9 Why PCIe for SSD Interface? 55
2.10 PCIe SSD Implementations 57
2.11 Standards Driving Broader Adoption of PCIe SSDs 60
References 61
Chapter 3: SAS and SATA SSDs 63
3.1 Introduction 63
3.2 Enterprise vs. Consumer SSDs 64
3.3 SAS vs. SATA Protocol 67
3.3.1 Connectivity and High Availability 69
3.3.2 Form Factor and Capacity 71
3.3.3 Performance 72
3.4 What's Ahead 75
References 76
Chapter 4: Hybrid Storage 77
4.1 NAND Flash Memory and HDD 77
4.2 External NAND =+ HDD 79
4.3 NAND on Motherboard =+ HDD 81
4.4 NAND/SSD =+ HDD 82
4.5 Hybrid SSD 85
4.6 Over-Provisioning 87
References 90
Chapter 5: NAND Flash Technology 94
5.1 Flash for SSD Application 94
5.2 Introduction to Floating Gate NAND Operation 95
5.2.1 The Floating Gate NAND Memory Structure 96
5.2.2 The Floating Gate Cell Capacitive Coupling Model 97
5.2.3 Program and Erase of a Single Floating Gate Cell 99
5.2.4 Program, Erase, and Read of FG Cells in the NAND String 104
5.2.4.1 NAND Cell Programming and Self-Boosted Program Inhibit (SBPI) 105
5.2.4.2 Erase and Read of FG Cells in the NAND String 108
5.3 Reliability of Floating Gate NAND Memory Cells 110
5.4 Scaling of Floating Gate NAND Memory Cells 113
5.4.1 Scaling of the Floating Gate Cell Geometry 114
5.4.2 Floating Gate Cell Cross-Coupling 116
5.4.3 Word Line to Word Line Leakage Current 119
5.4.4 Number of Stored Floating Gate Electrons 120
5.4.5 Random Telegraph Noise 122
5.5 Shrinking the Floating Gate NAND Technology Beyond the Direct Optical Lithography Limitation 124
5.6 Charge Trapping NAND Memory Cells as Floating Gate Cell Replacement 128
5.7 3D Memory Cell Integration for Future Mass Storage Applications 132
References 137
Chapter 6: NAND Flash Design 142
6.1 NAND Flash Memories 143
6.2 Logic Device View 143
6.2.1 Command Interface 144
6.2.2 Test Interface 145
6.2.3 Datapath 146
6.2.4 Microcontroller 148
6.3 NAND DDR Interface 149
6.3.1 DDR Interface 150
6.3.2 Power 152
6.3.3 Capacity 152
6.4 I/O Design 154
6.4.1 Basic CMOS Output Buffer Design 154
6.4.2 Simultaneous Switching Noise (SSN) 155
6.4.3 High Speed NAND I/O Design 157
6.4.4 Double Data Rate OCD 157
6.4.4.1 OCD Linearity: Push-Pull and Open-Drain Configurations 158
6.4.4.2 Slew Rate Control and Bandwidth 158
6.4.4.3 Voltage Domain Change: Level Shifting 158
6.4.4.4 Jitter Sources and Duty Cycle Distortion 159
6.5 Read Operation: The Sense Amplifier 159
6.5.1 Interleaving Architecture 164
6.5.2 All BitLine (ABL) Architecture 166
6.5.3 Read Voltage with Thermal Tracking 170
6.6 Program 172
6.7 Erase 174
6.8 MLC and XLC Storage 175
6.9 High Voltage Management 177
6.9.1 Charge Pumps 177
6.9.2 Internal Supply Voltage Regulator 180
6.9.3 Double-Supply Voltage Regulator 181
6.10 Wordline Decoder 182
References 184
Chapter 7: NAND and Controller Co-design for SSDs 187
7.1 Introduction 187
7.2 Analysis of SSD Performance 189
7.3 Selective Bit-Line Precharge Scheme 193
7.4 Advanced Source-Line Program 195
7.5 Intelligent Interleaving 198
7.6 Sector Size Optimization 199
7.7 Adaptive Program-Voltage Generator for 3D-SSD 202
7.8 Asymmetric Coding 207
7.9 Stripe Pattern Elimination Algorithm 211
7.10 Conclusions 213
References 214
Chapter 8: SSD Reliability 216
8.1 Introduction 216
8.2 Reliability at Physical Level 217
8.2.1 NAND Flash Endurance 218
8.2.2 NAND Data Retention 220
8.2.3 Erratic Bits and Over-Programming 222
8.2.4 Reliability Considerations on SLC/MLC NAND Architectures 223
8.3 Reliability at Architectural Level 225
8.4 Reliability at System Level 227
8.4.1 RAID Systems 228
8.4.2 Caching 229
8.5 Reliable Data Management in Power Failure Scenarios 230
8.5.1 Power Failure Circuitry in SSDs 230
8.5.2 Supercapacitors 231
8.5.3 Discrete Capacitors 232
8.6 Endurance and Retention Verification in SSDs 233
8.6.1 SSD Endurance and Retention Rating 234
8.6.2 Endurance and Retention Stress Methods 235
8.6.3 Direct Method 236
8.6.3.1 Sample Size 236
8.6.3.2 Endurance Stress 237
8.6.3.3 Retention Stress 240
8.6.4 Extrapolation Method 241
8.6.4.1 Accelerated Write Rate Through Modified Workload 242
8.6.4.2 Extrapolation of FFR and Bad-Block Trends 242
8.6.4.3 FFR and UBER Estimation from Reduced-Capacity SSDs 243
8.7 Evaluating SSD Reliability Versus HDD Reliability 243
References 244
Chapter 9: Efficient Wear Leveling in NAND Flash Memory 245
9.1 Introduction 246
9.2 Evenness-Aware Algorithm 248
9.2.1 Algorithm Design 248
9.2.1.1 Overview 248
9.2.1.2 Block Erasing Table 249
9.2.1.3 SW Leveler 250
9.2.2 Worst-Case Analysis 252
9.2.2.1 Worst-Case Model for Extra Overheads 252
9.2.2.2 Extra Block Erases 253
9.2.2.3 Extra Live-Page Copyings 253
9.3 Dual-Pool Algorithm 254
9.3.1 Algorithm Design 254
9.3.1.1 Algorithm Concept 254
9.3.1.2 The Dual-Pool Algorithm: A Basic Form 256
9.3.1.3 Pool Adjustment 257
9.3.1.4 Algorithm Demonstration 259
9.3.2 Case Study: An SSD Implementation of the Dual-Pool Algorithm 261
9.3.2.1 The Firmware and Disk Emulation 261
9.3.2.2 Block-Wearing Information and Priority Queues 264
9.3.2.3 Segment Check-In/Check-Out 265
9.4 Conclusion 267
References 267
Chapter 10: BCH for Solid-State-Drives 270
10.1 Error Correction Codes Basic Definitions 270
10.2 BCH Codes 275
10.3 BCH Decoding Failures 281
10.4 Detection Properties 282
10.5 BCH Weight Estimation 283
10.6 BCH Weight Estimation: Real Cases Analysis 290
10.6.1 BCH[255,207,13] 291
10.6.2 BCH[1023, 993,7] 291
10.6.3 BCH[4095, 3975,21] 293
10.6.4 BCH[16383, 15851,77] 295
10.7 BCH Detection Conclusion 296
10.8 Multi-channel BCH 299
References 302
Chapter 11: Low-Density Parity-Check (LDPC) Codes 304
11.1 Shannon Limit 304
11.1.1 Entropy and Mutual Information 304
11.1.2 System Model and Channel Capacity 305
11.1.3 The Channel Coding Theorem 309
11.2 Maximum a Posteriori and Maximum Likelihood Decoding of Linear Block Codes 311
11.3 NAND Flash Memory Channel Model 311
11.3.1 SLC Channel Model 312
11.3.2 MLC Channel Model 314
11.4 Low-Density Parity-Check Codes 316
11.4.1 LDPC Code Ensembles 317
11.4.2 QC-LDPC Codes Construction 319
11.4.3 Error Floor 320
11.5 Belief Propagation (BP) Decoding of LDPC Codes 321
11.5.1 Introduction 321
11.5.2 Preliminaries 322
11.5.3 Algorithm Description 324
11.5.3.1 Overview 324
11.5.3.2 Initialization 326
11.5.3.3 Horizontal Step 327
11.5.3.4 Vertical Step 328
11.5.3.5 Hard Decision and Stopping Criterion 329
11.5.4 Log-Domain BP Decoder 330
11.6 Reduced-Complexity Decoders 333
11.6.1 Min-Sum Decoder 333
11.6.2 Gallager B Decoder 334
11.6.3 Flipping Algorithms 337
11.7 Numerical Example 338
References 340
Chapter 12: Protecting SSD Data Against Attacks 343
12.1 Challenges of SSD Security vs. HDD 343
12.2 Introduction to Cryptography 346
12.2.1 Basic Concepts 347
12.2.2 Cryptanalysis 352
12.2.3 Hash Functions 355
12.3 AES 359
12.3.1 Key Generator 360
12.3.2 AES Algorithm Core 360
12.4 SSD Security and Applications 363
References 364
Chapter 13: Flash Signal Processing and NAND/ReRAM SSD 366
13.1 Error Prediction (EP) LDPC [1] 366
13.2 Error Recovery Scheme [1] 371
13.3 3D TSV-Integrated Hybrid ReRAM/MLC NAND SSD [10] 373
13.3.1 Data Management Algorithms [10] 376
13.3.2 Performance, Power and Reliability [10] 378
13.4 Conclusions 382
References 383
Index 384