Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms (eBook)

Francky Catthoor is a leading researcher at IMEC and is very well established within the EDA community. He is IEEE Fellow and has edited and authored 6 books for Springer/Kluwer.

Preface 5
Contents 9
1 Introduction 13
1.1 The System-on-Chip Era 14
1.2 Characteristics of Embedded Software 17
1.3 Context and Motivation 21
1.4 TCM Framework 24
1.5 Overview of Chapters 25
2 Related Work 27
2.1 Real-time Scheduling 27
2.2 Low-power Considerations 34
2.3 Platform Issues and Codesign Framework 41
3 System Model and Work Flow 46
3.1 Overview of TCM Work flow 46
3.2 Gray-Box Model 48
3.3 System Scenario Selection 54
3.4 Two-Phase Scheduling 56
3.5 Summary 59
4 Basic Design-Time Scheduling 61
4.1 Problem Formulation 61
4.2 Exact Scheduling Algorithms 63
4.3 Forward Search Algorithm 65
4.4 Backward Search Algorithm 99
4.5 Subplatform Scheduling 108
4.6 Handling Timing-Constraints 114
4.7 Summary 117
5 Scalable Design-Time Scheduling 118
5.1 Introduction 118
5.2 Motivational Example 119
5.3 Thread Frame Decomposition 123
5.4 Thread Partition Clustering 132
5.5 Thread Partition Interleaving 133
5.6 Experimental Results and Discussions 137
5.7 Comparison with State of the Art 139
5.8 Summary 142
6 Fast and Scalable Run-time Scheduling 143
6.1 Two-Phase Task Scheduling: Why and How 143
6.2 Run-Time Scheduling Algorithm 149
6.3 Experimental Results 154
6.4 Summary 158
7 Handling of Multidimensional Pareto Curves 159
7.1 Overview of the Customized Run-Time Management 160
7.2 Problem Formulation of Run-Time Operating Point Selector 163
7.3 Related Work 164
7.4 MP-SoC Heuristic Description 165
7.5 Experimental Results 168
7.6 Summary 170
8 Run-Time Software Multithreading 171
8.1 Motivation of Run-Time Rescheduling 172
8.2 Run-Time Interleaving 174
8.3 Experimental Results and Discussion 181
8.4 Comparison with State of the Art 182
8.5 Summary 184
9 Fast Source-level Performance Estimation 185
9.1 Introduction 185
9.2 Motivational Example 187
9.3 Comparison with State of the Art 190
9.4 Fundamentals of the Estimation Technique 192
9.5 Experimental Results 199
9.6 Summary 201
10 Handling of Task-Level Data Communication and Storage 202
10.1 Memory Architecture 203
10.2 Exploring Thread Node Level Data Reuse 207
10.3 Data Assignment on L1 Memory Layer 208
10.4 Bandwidth Aware Scheduling 219
10.5 Handling inter-TN and inter-TF Data Transfers 226
10.6 Summary 230
11 Demonstration on Heterogeneous Multiprocessor SoCs 232
11.1 Motivation for Heterogeneous Multiprocessor Platforms 232
11.2 Mapping Visual Texture Coding Decoder 233
11.3 Summary 243
12 Conclusions and future research work 245
A Input and output data of scheduling examples in Section 4.3.1 249
References 254