Extreme Low-Power Mixed Signal IC Design (eBook)
XXXIV, 274 Seiten
Springer New York (Verlag)
978-1-4419-6478-6 (ISBN)
Design exibility and power consumption in addition to the cost, have always been the most important issues in design of integrated circuits (ICs), and are the main concerns of this research, as well. Energy Consumptions: Power dissipation (P ) and energy consumption are - diss pecially importantwhen there is a limited amountof power budgetor limited source of energy. Very common examples are portable systems where the battery life time depends on system power consumption. Many different techniques have been - veloped to reduce or manage the circuit power consumption in this type of systems. Ultra-low power (ULP) applications are another examples where power dissipation is the primary design issue. In such applications, the power budget is so restricted that very special circuit and system level design techniquesare needed to satisfy the requirements. Circuits employed in applications such as wireless sensor networks (WSN), wearable battery powered systems [1], and implantable circuits for biol- ical applications need to consume very low amount of power such that the entire system can survive for a very long time without the need for changingor recharging battery[2-4]. Using newpowersupplytechniquessuchas energyharvesting[5]and printable batteries [6], is another reason for reducing power dissipation. Devel- ing special design techniques for implementing low power circuits [7-9], as well as dynamic power management (DPM) schemes [10] are the two main approaches to control the system power consumption. Design Flexibility: Design exibility is the other important issue in modern in- grated systems.
Extreme Low-Power Mixed Signal IC Design 3
Contents 7
List of Figures 13
List of Tables 27
Acknowledgments 29
Acronyms 31
Chapter 1: Introduction 35
1.1 Applications of Widely Adjustable Circuits and Systems 36
1.1.1 Performance Scalability and Requirements 39
1.2 Prior Art 40
1.2.1 Digital Circuits 40
1.2.1.1 Static CMOS Logic 40
1.2.1.2 Other Logic Styles 41
1.2.2 Analog Circuits 42
1.2.2.1 Circuits Using Switchable (Programmable) Components 42
1.2.2.2 Switched-Capacitor Circuits 43
1.2.2.3 Log-Domain Circuits 44
1.3 Organization 44
References 45
Chapter 2: Subthreshold MOS for Ultra-Low Power 48
2.1 MOS Technology 48
2.2 Device Modeling 49
2.2.1 I–V Characteristics 49
2.2.2 Second Order Effects 52
2.2.2.1 Mobility Reduction Due to Vertical Field 52
2.2.2.2 Velocity Saturation 53
2.2.2.3 Channel Length Modulation 53
2.3 Design Considerations in Subthreshold 54
2.3.1 PVT Variation 54
2.3.2 Matching 56
2.3.2.1 Physical Mechanism of VT Fluctuation 57
2.3.2.2 Mismatch due to Gate Leakage 58
2.3.3 Noise 59
2.3.3.1 Noise Efficiency Factor 60
2.3.3.2 Noise Due to the Gate Leakage 61
2.4 Ultra-Low-Power Design Using Subthreshold MOS 62
2.4.1 MOS Transistor Leakage Mechanisms 63
2.4.1.1 Scaling Rules 63
2.4.1.2 Gate Tunneling 64
2.4.1.3 Subthreshold Conducting 65
2.4.1.4 PN Junction 65
2.4.1.5 DIBL 66
2.4.1.6 GIDL 67
2.4.1.7 Hot Carrier 68
2.4.1.8 Punchthrough 68
2.4.1.9 Channel Length Effect 68
2.4.1.10 Narrow-Width Effect 68
2.4.1.11 Thermal Effect 68
2.4.1.12 Short Circuit Current 69
2.4.2 Leakage Reduction Techniques 69
2.4.2.1 Device Level Engineering 69
2.4.2.2 Circuit Level Techniques 69
2.5 Impacts of Variation on Subthreshold CMOS Operation 70
2.5.1 Noise Margin 72
2.5.2 Energy Consumption 78
2.5.3 Optimal Design with Technology Scaling 82
2.5.3.1 A Low Activity Rate System Example 82
2.5.3.2 A High Activity Rate System Example 84
2.5.3.3 Discussion 85
2.5.4 Supply Voltage and Threshold Voltage Scaling for Optimal Design 86
References 89
Part I Scalable and Ultra-Low-Power Digital Integrated Circuits 92
Chapter:3: Subthreshold Source-Coupled Logic 93
3.1 Introduction 93
3.2 Conventional SCL Topology 95
3.2.1 Circuit Topology 95
3.2.2 Tradeoffs in Design of Strong-Inversion SCL Gates 99
3.3 Ultra-Low-Power Source-Coupled Logic 102
3.3.1 High-Valued Load Device Concept 102
3.3.1.1 DC Characteristics of the Load Devices 104
3.3.1.2 Floating High-Valued Resistance 106
3.3.2 STSCL Gates 106
3.4 Design Issues and Performance Estimation 108
3.4.1 Power-Speed Tradeoffs in STSCL 108
3.4.2 Noise Margin 111
3.4.3 Replica Bias Circuit 115
3.4.4 Minimum Operating Current 116
3.4.5 Global Process and Temperature Variation 118
3.4.6 Effect of Mismatch on Delay 119
3.4.7 Minimum Supply Voltage 121
3.5 Experimental Results 121
3.5.1 Basic Building Blocks 121
3.5.2 Ring Oscillator and Frequency Divider 122
3.5.2.1 Ring Oscillator Test Circuit 123
3.5.2.2 Divider Test Circuit 124
3.5.3 Multiplier Circuit 126
3.6 Conclusion 127
References 128
Chapter 4: STSCL Standard Cell Library Development 130
4.1 Introduction 130
4.2 Standard Cell Library 131
4.2.1 Background 131
4.2.2 Cell Types 132
4.2.3 Cell Layout 132
4.2.4 Characterization 134
4.2.5 LEF File 135
4.2.6 Template Generation 135
4.3 Design Strategies 136
4.3.1 Series–Parallel Tail Bias Transistors 137
4.3.2 Constant Area Scaling 138
4.4 Demonstration Circuits 139
4.4.1 FIR Filter Topology 139
4.4.2 Sample FIR Filter Demonstrator Circuit 140
4.4.2.1 FIR Filter in CMOS 0.18m 140
4.4.2.2 FIR Filter in CMOS 90nm 142
4.5 Conclusion 143
References 144
Chapter 5: Subthreshold Source-Coupled Logic Performance Analysis 145
5.1 Introduction 145
5.2 Comparison with the CMOS Topology 146
5.2.1 Ultra-Low-Power Requirements 146
5.2.2 Power-Speed Tradeoff in STSCL 147
5.2.3 Performance Analysis of CMOS Logic Circuits 148
5.2.4 Performance Comparison 151
5.3 Performance Improvement Techniques 152
5.3.1 Compound Logic Style 153
5.3.2 Using Source-Follower Buffer 155
5.3.2.1 Proposed Topology 155
5.3.2.2 Performance Analysis 156
5.3.2.3 Optimized Design 159
5.3.3 Pipelining Technique 160
5.4 Experimental Results 163
5.4.1 STSCL with Source-Follower Buffer 163
5.4.2 Pipelined Adder Chain 164
5.4.3 Pipelined Multiplier 165
5.5 Conclusions 167
References 168
Chapter 6: Low-Activity-Rate and Memory Circuits in STSCL 170
6.1 Introduction 170
6.2 Power Efficiency in Low Activity Rates 171
6.2.1 STSCL Topology Performance 171
6.2.2 CMOS Topology Performance 173
6.2.3 Comparison 174
6.3 Low-Leakage CMOS SRAMs 175
6.4 Low Stand-By Current STSCL Memory Cell 178
6.4.1 Circuit Topology 178
6.4.2 Device Sizing 180
6.4.3 Sense Amplifier 181
6.4.4 Leakage Current Detection 182
6.5 Experimental Results 182
6.6 Observations and Discussion 185
References 186
Part II Scalable and Ultra-Low-Power Analog Integrated Circuits 188
Chapter 7: Widely Adjustable Continuous-Time Filter Design 189
7.1 Introduction 189
7.2 Amplifier Design 190
7.2.1 Low Power Folded-Cascode Amplifier 190
7.2.2 Widely Adjustable Two-Stage Amplifier 192
7.3 Transconductor-C Filter Design 194
7.3.1 Proposed Biquadratic Filter Topology 194
7.3.1.1 Proposed Circuit Topology 195
7.3.2 Dynamic Range 198
7.3.3 Sixth Order gm-C Filter 199
7.4 MOSFET-C Filter Design 199
7.4.1 Circuit Topology 200
7.4.2 High-Valued Pseudo-Resistance 200
7.4.3 Dynamic Range 203
7.4.4 Second Order MOSFET-C Filter 205
7.5 Experimental Results 206
7.5.1 MOSFET-C Filter 206
7.5.2 gm-C Filter 208
7.5.3 Figure of Merit 210
7.6 Conclusion 211
References 212
Chapter 8: Scalable Folding and Interpolating ADC Design 214
8.1 Introduction 214
8.2 Previous Art 214
8.3 Folding and Interpolating Analog-to-Digital Converter 216
8.3.1 Basics 216
8.3.1.1 Nonideality Effects in FAI ADCs 218
8.3.2 Building Blocks and Design Tradeoffs 219
8.3.2.1 Resistor Ladder 219
8.3.2.2 Offset Effect on Linearity 221
8.3.2.3 Offset Effect on Speed and Power 224
8.4 Design of FAI ADC 225
8.4.1 Circuit Topology 226
8.4.2 Ultra Low Power Resistor Ladder 229
8.4.3 Comparator Circuit 231
8.4.4 Encoder 233
8.5 Simulation and Experimental Results 236
8.5.1 Encoder 236
8.5.2 FAI ADC Performance 237
8.6 Conclusion 238
References 239
Chapter 9: Widely Adjustable Ring Oscillator Based ADC 241
9.1 Introduction 241
9.2 Background 241
9.2.1 Dynamic Range 241
9.2.2 Improving the Resolution 243
9.3 Performance Scalability in Ring Oscillator Based ADCs 244
9.3.1 Frequency Domain Adjustability 244
9.3.2 Dynamic Range Adjustment 248
9.4 Top Level Design 249
9.4.1 Sources of Non-Ideality 249
9.4.1.1 Delay Mismatch 249
9.4.1.2 Ring Oscillator Jitter 250
9.4.1.3 Sampling Clock Jitter 250
9.4.1.4 Comparator Meta-Stability Effect 251
9.4.2 Performance Analysis 252
9.5 Circuit Design 254
9.5.1 Ring Oscillator 254
9.5.1.1 Delay Matching 254
9.5.1.2 Oscillator Jitter 256
9.5.2 Logic Circuit 257
9.5.3 Current-Mode Integrator 257
9.6 High Order Modulator Design 259
9.6.1 Analysis and Modeling 259
9.6.2 Behavioral Modeling 263
9.7 Simulations and Experimental Results 266
9.8 Conclusion and Discussion 267
References 268
Chapter 10: Wide Tuning Range PLL 269
10.1 Introduction 269
10.2 Wide Tuning Range PLLs 269
10.2.1 Background 270
10.2.2 Wide Tuning Range CPLL 272
10.2.3 Design Issues with Wide Tune PLLs 275
10.3 Circuit Design 276
10.3.1 Proposed PLL Topology 276
10.3.2 Ring Oscillator 278
10.3.3 Frequency Divider and Phase-Frequency Detector (PFD) 279
10.3.4 Transconductor 280
10.4 Simulation and Experimental Results 280
10.5 Conclusions 284
References 284
Chapter 11: Conclusions 286
11.1 Main Contributions 287
11.2 Perspectives 289
References 290
Index 292
| Erscheint lt. Verlag | 14.9.2010 |
|---|---|
| Zusatzinfo | XXXIV, 274 p. |
| Verlagsort | New York |
| Sprache | englisch |
| Themenwelt | Informatik ► Weitere Themen ► CAD-Programme |
| Technik ► Elektrotechnik / Energietechnik | |
| Schlagworte | Circuit Design • Circuits and Systems • CMOS • Embedded Systems • Extreme Low-Power Circuit Design • Filter • Integrated circuit • Low-Power Circuit Design • Low-Power CMOS VLSI • Low-Power Mixed Signal Circuit Design • Modeling • Subthreshold Design • Subthreshold source-couple • Subthreshold source-coupled logic • Ultra Low-Powe • Ultra Low-Power Circuit Design |
| ISBN-10 | 1-4419-6478-9 / 1441964789 |
| ISBN-13 | 978-1-4419-6478-6 / 9781441964786 |
| Haben Sie eine Frage zum Produkt? |
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