Voltage Regulators for Next Generation Microprocessors (eBook)

Voltage Regulators for Next Generation Microprocessors 3
Preface 7
Abstract 11
Contents 13
Abbreviations 19
Chapter 1: Introduction 27
1.1 The Microprocessor Load 27
1.2 The Microprocessor Power Supply 35
1.2.1 Voltage Regulator (VR) Specifications 35
1.2.1.1 VR Guidelines for Servers and Workstations 38
1.2.1.2 VR Guidelines for Notebooks 38
1.2.1.3 The DrMOS Specification 39
1.2.2 Basic Circuit Topology 39
1.2.3 System Architecture 41
1.2.4 Semiconductor Power Devices 43
1.2.4.1 Device Modeling and Optimization Tools 47
1.2.5 Gate Driving Schemes 48
1.2.6 Filters 51
1.2.6.1 Input Filter 52
1.2.6.2 Output Filter 53
1.2.7 Control Systems 57
1.2.7.1 Load Line Regulation 58
1.2.7.2 Multiphase Regulation 61
1.2.7.3 Multimode Switching Modulation 63
1.2.7.4 Gate Driving Control 63
1.2.8 Packaging and Integration 65
1.2.9 Commercial Voltage Regulators 67
1.2.10 Survey on Power MOSFET Models for Circuit Simulations 71
1.3 Objectives of the Thesis 74
1.4 Methodological Approach 75
1.5 Thesis Outline 79
References 80
Chapter 2: Model Level 0: Switching Behavior of Power MOSFETs 92
2.1 Power MOSFET Model for Circuit Simulations 93
2.1.1 Model Structure and Implementation 94
2.1.2 Model Data Acquisition 100
2.1.2.1 Gate Resistance and Package Impedances 100
2.1.2.2 DC Output Characteristics 105
2.1.2.3 Interelectrode Capacitances 107
2.1.2.4 Body Diode Reverse Recovery 112
2.2 Switched Converter Test Board 115
2.2.1 Gate Driver 116
2.2.2 Input/Output Filters 119
2.2.3 PCB Layout Impedance Characterization 120
2.3 Switched Converter Simulation Setup 122
2.4 Model Validation 126
2.5 Analysis of Switching Behavior 137
2.5.1 Loss Breakdown 138
2.5.1.1 Switching Time Subintervals 139
CHS and RR at LE Transition (t1-t3) 141
VHS at LE Transition (t3-t4) 142
VHS at FE Transition (t5-t6) 143
CHS at FE Transition (t6-t7) 143
2.5.1.2 Identification of Switching Loss Mechanisms 143
Load Current Hard-Switching (or Snubbed Hard-Switching SHS) 143
Half-Bridge Charging (Both Capacitive and Inductive) 144
Gate Charging 144
Reverse Recovery 144
Gate Bounce 145
Avalanche Breakdown 145
2.5.1.3 Loss Quantification 145
2.5.2 Influence of the Body-Effect on Switching Losses 147
2.5.2.1 Impact on Reverse Recovery 149
2.5.2.2 Impact on Gate Bounce 151
2.5.3 Loss Analysis of a Multichip Module 153
References 156
Chapter 3: Model Level 1: Piecewise Linear Analytical Switching Model 158
3.1 Modeling Approach 159
3.2 Hard-Switching Model 166
3.2.1 Leading Edge Transition 168
3.2.2 Falling Edge Transition 172
3.2.3 Leading and Falling Edge Transitions Tradeoffs 175
3.3 Leading Edge Switched-Node Ringing 180
3.3.1 Charging Loss 184
3.3.2 Overvoltage Stress 186
3.3.3 Avalanche Breakdown 187
3.3.4 Reverse Recovery 191
3.3.5 Gate Bounce 194
3.4 Falling Edge Ringing Transition 205
3.4.1 Charging Loss 209
3.4.2 Overvoltage Stress 213
3.4.3 Avalanche Breakdown 215
3.5 Gate Driving 215
3.6 Model Validation 216
References 220
Chapter 4: Model Level 2: Power Loss Model 221
4.1 Power MOSFET Losses 222
4.1.1 Half-Bridge Charging Loss 222
4.1.2 Gate Charging Loss 223
4.1.3 Load Current Hard-Switching 225
4.1.3.1 LE Transition 226
4.1.3.2 FE Transition 227
4.1.4 Load Current ON Conduction 229
4.2 Losses of Gate Drive Switches 231
4.3 Filter Loss 232
4.4 PCB Loss 233
4.5 Model Validation 234
References 236
Chapter 5: Model Level 3: Optimization 237
5.1 Output Filter 237
5.1.1 Steady-State Output Ripple 238
5.1.2 Load Line Transient 241
5.1.2.1 Output Current Slew Rate 243
5.1.2.2 Output Inductors´ Discharge 244
5.1.3 Component Selection Procedure 247
5.2 Input Filter 250
5.3 Power MOSFETs and Gate Drivers 252
5.3.1 Design Guidelines 255
5.3.2 Optimization Case Example 256
5.4 Selection of Fs, Lo, and Np 259
5.4.1 Case-Example 1: State-of-the-Art Desktop Application 259
5.4.2 Case Example 2: State-of-the-Art Laptop Application 263
References 267
Chapter 6: Roadmap Targets 268
6.1 Power Switches 269
6.1.1 State-of-the-Art Trench4 MOSFET Technology 270
6.1.2 Trench6 MOSFET Technology 276
6.1.3 Next Generation Technologies 283
6.2 Gate Drivers 286
6.3 Packaging 289
6.4 Passive Filters 289
6.5 Control 291
6.6 Layout Arrangement 292
6.7 Mobile Laptop Applications 298
References 300
Chapter 7: Conclusions and Future Work 302
Appendix A: Third Quadrant DC Output Characteristics of Low Voltage Trench MOSFETs 307
A.1 DC Output Characteristics 307
A.2 Device Physics Simulations vs. Measurement Results 309
A.3 Comparison of the First and 3Q DC Output Characteristics 309
A.4 3Q Current Flow Through a Trench Cell 313
References 320
Appendix B: Reverse Recovery in LV Trench MOSFETs 322
B.1 Impact of the Body-Effect in Reverse Recovery Transients 322
B.2 Reverse Recovery Circuit Model 325
B.3 SPICE Simulations of a Synchronous Buck Converter 328
B.4 Summary 332
References 332
Appendix C: Reverse Recovery Lumped Models 333
C.1 Device Physics Simulations of Power Trench MOSFETs 334
C.2Circuit Simulator Lumped Models 337
C.2.1Transmission Line Based Lumped Model 337
C.2.2 Lumped Model Based on Two Lumped Storage Nodes 339
C.2.3 Empirical Lumped Model 340
C.3 Models Performance 341
C.4 Summary 344
References 345
Appendix D: Loss Quantification 346
D.1 Conceptual Approach 346
D.2 Implementation 348
D.3 Loss Mechanisms Formulation 350
D.3.1 Load Current Hard-Switching 350
D.3.2 Half-Bridge Charging 351
D.3.3 Gate Charging 351
D.3.4 Reverse Recovery 352
D.3.5 Gate Bouncing 352
D.3.6 Avalanche Breakdown 352
D.3.7 Output Current ON Conduction 353
Appendix E: Magnetic Losses 354
E.1 Quasi-Static Formulation 354
E.2 PCB Layout 355
E.3 Power MOSFET Package: LFPak 362
E.4 Power Coil 364
E.4.1 Classical Eddy Current Loss Model 367
E.4.2 Hysteresis Loss Model 367
E.4.3 Excess Loss Model 370
E.4.4 Simulation Results 371
References 374
Appendix F: Quality Factor in Resonant Gate Drivers 376
F.1 Gate Driver Requirements 377
F.2 Formulation of Basic Resonant Gate Driver Topologies 380
F.2.1 Basic Resonant Gate Driver Topologies 380
F.2.2 Assumptions and Definitions 380
F.2.3 Resonant Gate Driver (a) 381
F.2.4 Resonant Gate Driver (b) 382
F.2.5 Resonant Gate Driver (c) 383
F.2.6 Resonant Gate Driver (d) 385
F.3 Topology Comparison 386
F.4 Application Example 388
F.5 Experimental Results 392
F.6 Discussion and Conclusions 392
References 392
Appendix G: Experimental Prototypes 394
G.1 Synchronous Buck Converter Board 394
G.2 Point-of-Load Demo Board 401
G.3 Multiphase VR Demo Board 405
Index 414