Nanoscale Memory Repair (eBook)

Nanoscale Memory Repair 3
Preface 5
Contents 7
Chapter 1: An Introduction to Repair Techniques 11
1.1 Introduction 11
1.2 Hard and Soft Errors and Repair Techniques 11
1.2.1 Hard and Soft Errors 12
1.2.2 Redundancy 13
1.2.3 ECC 15
1.2.4 Combination of Redundancy and ECC 18
1.2.5 Others 18
1.3 Margin Errors and Repair Techniques 19
1.3.1 Device and Process Variations 21
1.3.2 Timing and Voltage Margin Errors 21
1.3.3 Reductions of Margin Errors 24
1.4 Speed-Relevant Errors and Repair Techniques 25
References 26
Chapter 2: Redundancy 28
2.1 Introduction 28
2.2 Models of Fault Distribution 29
2.2.1 Poisson Distribution Model 29
2.2.2 Negative-Binomial Distribution Model 31
2.3 Yield Improvement Through Redundancy 34
2.4 Replacement Schemes 38
2.4.1 Principle of Replacement 38
2.4.2 Circuit Implementations 39
2.5 Intrasubarray Replacement 45
2.5.1 Simultaneous and Individual Replacement 48
2.5.2 Flexible Replacement 51
2.5.3 Variations of Intrasubarray Replacement 58
2.6 Intersubarray Replacement 61
2.7 Subarray Replacement 63
2.8 Devices for Storing Addresses 65
2.8.1 Fuses 65
2.8.2 Antifuses 67
2.8.3 Nonvolatile Memory Cells 69
2.9 Testing for Redundancy 70
References 73
Chapter 3: Error Checking and Correction (ECC) 77
3.1 Introduction 77
3.2 Linear Algebra and Linear Codes 78
3.2.1 Coding Procedure 78
3.2.2 Decoding Procedure 80
3.3 Galois Field 83
3.4 Error-Correcting Codes 85
3.4.1 Minimum Distance 86
3.4.2 Number of Check Bits 87
3.4.3 Single Parity Check Code 90
3.4.4 Hamming Code 90
3.4.5 Extended Hamming Code and Hsiao Code 92
3.4.6 Bidirectional Parity Code 93
3.4.7 Cyclic Code 94
3.4.8 Nonbinary Code 97
3.5 Coding and Decoding Circuits 100
3.5.1 Coding and Decoding Circuits for Hamming Code 100
3.5.2 Coding and Decoding Circuits for Cyclic Hamming Code 105
3.5.3 Coding and Decoding Circuits for Nonbinary Code 110
3.6 Theoretical Reduction in Soft-Error and Hard-Error Rates 113
3.6.1 Reduction in Soft-Error Rate 113
3.6.1.1 Single-Error Correction 114
3.6.1.2 Double-Error Correction 115
3.6.2 Reduction in Hard-Error Rate 116
3.6.2.1 Single-Error Correction 116
3.6.2.2 Double-Error Correction 118
3.7 Application of ECC 119
3.7.1 Application to Random-Access Memories 120
3.7.1.1 ECC Using Bidirectional Parity Code 120
3.7.1.2 ECC Using (Extended) Hamming Code 123
3.7.1.3 Multicell Error Problem 127
3.7.1.4 Partial-Write Problem 130
3.7.1.5 Startup Problem 133
3.7.2 Application to Serial-Access Memories 134
3.7.3 Application to Multilevel-Storage Memories 138
3.7.4 Application to Other Memories 141
3.7.4.1 Mask ROMs 141
3.7.4.2 Content Addressable Memories (CAMs) 142
3.8 Testing for ECC 143
References 144
Chapter 4: Combination of Redundancy and Error Correction 146
4.1 Introduction 146
4.2 Repair of Bit Faults Using Synergistic Effect 146
4.2.1 Principle of Synergistic Effect 146
4.2.2 Yield Estimation 151
4.2.2.1 Row Redundancy 151
4.2.2.2 Column Redundancy 153
4.2.2.3 Row and Column Redundancies 156
4.3 Application of Synergistic Effect 156
4.3.1 Threshold-Voltage Variations 156
4.3.2 Estimated Effect 158
References 162
Chapter 5: Reduction Techniques for Margin Errors of Nanoscale Memories 163
5.1 Introduction 163
5.2 Definition of Vmin 165
5.3 Reduction of Vmin for Wider Margins 166
5.3.1 General Features of Vmin 166
5.3.1.1 MOSFETs Governing Vmin 166
5.3.1.2 Lowest Necessary Vt (Vt0) 169
5.3.1.3 Parameter gamma 170
5.3.1.4 Maximum Deviation, DeltaVtmax 170
5.3.2 Comparison of Vmin for Logic Block, SRAMs, and DRAMs 171
5.4 Advanced MOSFETs for Wider Margins 171
5.4.1 Planar FD-SOI MOSFETs 173
5.4.2 FinFETs 175
5.5 Logic Circuits for Wider Margins 179
5.5.1 Gate-Source Offset Driving 180
5.5.2 Gate-Source Differential Driving 184
5.5.3 Combined Driving 186
5.5.4 Instantaneous Activation of Low-Vt0 MOSFETs 187
5.5.5 Gate Boosting of High-Vt0 MOSFETs 187
5.6 SRAMs for Wider Margins 188
5.6.1 Ratio Operations of the 6-T Cell 188
5.6.2 Shortening of Datalines and Up-Sizing of the 6-T Cell 189
5.6.3 Power Managements of the 6-T Cell 191
5.6.4 The 8-T Cell 193
5.7 DRAMs for Wider Margins 194
5.7.1 Sensing Schemes 194
5.7.2 Vmin(SA) of Sense Amplifier 195
5.7.3 Vmin(Cell) of Cell 196
5.7.4 Comparison Between Vmin(SA) and Vmin(Cell) 196
5.7.5 Low-Vt0 Sense Amplifier 197
5.7.6 FD-SOI Cells 198
5.8 Subsystems for Wider Margins 200
5.8.1 Improvement of Power Supply Integrity 200
5.8.2 Reduction in Vt0 at Subsystem Level 201
5.8.3 Low-Vt0 Power Switches 202
References 204
Chapter 6: Reduction Techniques for Speed-Relevant Errors of Nanoscale Memories 208
6.1 Introduction 208
6.2 Reduction Techniques for Speed-Degradation Errors 209
6.3 Reduction Techniques for Interdie Speed-Variation Errors 210
6.3.1 On-Chip VBB Compensation 212
6.3.2 On-Chip VDD Compensation and Others 216
References 217
Index 218