Network-on-Chip Architectures (eBook)

FM.pdf 1
1.pdf 21
Chapter 1 21
Introduction 21
1.1 The Diminishing Returns of Instruction-Level Parallelism 21
1.2 The Dawn of the Communication-Centric Revolution 22
1.3 The Global Wiring Challenge 22
1.4 The Network-on-Chip (NoC) Solution 24
1.5 Overview of Research 26
1.5.1 Legend for Figs. 1.4 and 1.5 27
2.pdf 33
Chapter 2 33
A Baseline NoC Architecture 33
3.pdf 37
Chapter 3 38
ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39] 38
3.1 Importance of Buffer Size and Organization 38
3.2 Related Work in Buffer Design 41
3.3 The Proposed Dynamic Virtual Channel Regulator (ViChaR) 43
3.3.1 Variable Number of Virtual Channels 46
3.3.2 ViChaR Component Analysis 49
3.4 Simulation Results 54
3.4.1 Simulation Platform 54
3.4.2 Analysis of Results 54
3.5 Chapter Summary 58
4.pdf 60
Chapter 4 60
RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Ne 60
4.1 Introduction and Motivation 60
4.2 Related Work in Partitioned Router Architectures 62
4.3 The Proposed Row–Column (RoCo) Decoupled Router 63
4.3.1 Row–Column Switch 63
4.3.2 Blocking Delay 67
4.3.3 Concurrency Control for High-Contention Environments 69
4.3.4 Flexible and Reusable On-Chip Communication 70
4.4 Fault-Tolerance Through Hardware Recycling 70
4.5 Performance Evaluation 75
4.5.1 Simulation Platform 75
4.5.2 Energy Model 76
4.5.3 A Performance, Energy, and Fault-Tolerance (PEF) Metric 76
4.5.4 Performance Results 77
4.6 Chapter Summary 81
5.pdf 84
Chapter 5 84
Exploring FaultoTolerant Network-on-Chip Architectures [37] 84
5.1 Introduction and Motivation 84
5.2 Simulation Platform Preliminaries 86
5.3 Handling Link Soft Faults 87
5.3.1 Flit-Based HBH Retransmission Scheme 88
5.3.2 Deadlock Recovery 91
5.3.2.1 Proposed Deadlock Recovery Scheme 91
5.3.2.2 Probing for Deadlock Detection and Recovery 95
5.4 Handling Soft Errors in Intra-Router Logic 96
5.4.1 Virtual Channel Arbiter Errors 97
5.4.2 Routing Computation Unit Errors 99
5.4.3 Switch Allocator Errors 100
5.4.4 Crossbar Errors 102
5.4.5 Retransmission Buffer Errors 102
5.4.6 Handshaking Signal Errors 102
5.5 Handling Hard Faults 102
5.5.1 Proximity-Aware (PA) Fault-Tolerant Routing Algorithm 103
5.5.2 Extension of PA Routing for Hot-Spot Avoidance 105
5.5.3 Service-Oriented Networking (SON) 107
5.5.4 SON – Direction Lookup Table (DLT) and Service Information Provider (SIP) 108
5.6 Chapter Summary 110
6.pdf 112
Chapter 6 112
On the Effects of Process Variation in Network-on-Chip Architectures [45] 112
6.1 Introduction and Motivation 112
6.2 Related Work in Process Variation (PV) 113
6.3 The Impact of PV on NoC Architectures 114
6.3.1 Evaluation Platform 114
6.3.2 PV Effects on Router Components 117
6.3.2.1 Input Buffers 117
6.3.2.2 Virtual Channel Arbitration (VA) and Switch Allocation (SA) 119
6.3.2.3 Crossbar (XBAR)/Links 124
6.4 The Proposed SturdiSwitch Architecture 124
6.4.1 IntelliBuffer: A Leakage-Aware Elastic Buffer Structure 125
6.4.2 VA Compaction Mechanism 127
6.4.3 SA Folding Mechanism 130
6.5 Chapter Summary 134
7.pdf 135
Chapter 7 136
The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15] 136
7.1 Introduction and Motivation 136
7.2 Exploration of Existing On-Chip Bus Architectures 138
7.2.1 Traditional Bus Architectures 138
7.2.1.1 Bus Segmentation 139
7.2.1.2 Bus Arbitration 139
7.2.2 TDMA Buses and Hybrid Interconnects 140
7.2.3 Constraints of Traditional Buses 141
7.2.4 CDMA Interconnects 142
7.3 The Dynamic Time-Division Multiple-Access (dTDMA) Bus 144
7.3.1 Operation of the Dynamic Timeslot Allocation 145
7.3.2 Implementation of the dTDMA Bus 146
7.3.3 Comparison with a Traditional Bus Architecture 147
7.3.4 dTDMA Bus Performance 149
7.3.4.1 Throughput 149
7.3.4.2 Average Latency 150
7.3.4.3 Arbitration Policy 152
7.3.4.4 Power Consumption 154
7.4 Comparison with Networks-on-Chip 155
7.4.1 Experimental Setup 155
7.4.2 Results 156
7.5 Interconnect Hybridization 158
7.5.1 Affinity Grouping 159
7.5.2 Simulation Methodology 160
7.5.3 Hybridization Results 161
7.6 Chapter Summary 163
8.pdf 164
Chapter 8 164
Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43] 164
8.1 Introduction and Motivation 166
8.2 Background 166
8.2.1 NUCA Architectures 167
8.2.2 Network-In-Memory (NetInMem) 167
8.2.3 Three-Dimensional (3D) Design and Architectures 168
8.3 A 3D NetInMem Architecture 170
8.3.1 The dTDMA Bus as a Communication Pillar 172
8.3.2 CPU Placement 174
8.4 3D L2 Cache Management 179
8.4.1 Processors and L2 Cache Organization 179
8.4.2 Cache Management Policies 180
8.4.2.1 Search Policy 180
8.4.2.2 Placement and Replacement Policy 180
8.4.2.3 Cache Line Migration Policy 181
8.5 Experimental Evaluation 181
8.5.1 Methodology 181
8.5.2 Results 183
8.6 Chapter Summary 186
9.pdf 188
Chapter 9 188
A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44] 188
9.1 Introduction and Motivation 190
9.2 Three-Dimensional Network-on-Chip Architectures 193
9.2.1 A 3D Symmetric NoC Architecture 193
9.2.2 The 3D NoC-Bus Hybrid Architecture 194
9.2.3 A True 3D NoC Router 196
9.2.4 A Partially-Connected 3D NoC Router Architecture 199
9.3 The Proposed 3D Dimensionally-Decomposed (DimDe) NoC Router Architecture 199
9.4 Performance Evaluation 207
9.4.1 Simulation Platform 207
9.4.2 Energy Model 208
9.4.3 Performance Results 208
9.5 Chapter Summary 213
10.pdf 215
Chapter 10 215
Digest of Additional NoC MACRO-Architectural Research 215
10.1 A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects [42] 215
10.2 Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects [46] 217
10.3 Exploring the Effects of Data Compression in NoC Architectures [47] 219
11.pdf 222
Chapter 11 222
Conclusions and Future Work 222
BM.pdf 225
Anchor 1 225