Advanced Test Methods for SRAMs (eBook)

Acknowledgements 4
Advanced Test Solutions for Dynamic Faults in SRAM Memories 5
Authors of the book: 5
Summary and objective of the book: 5
Contents 6
General Introduction 9
History 9
SRAMs 10
Test of SRAMs 10
Organization of the Book 10
Description of Each Chapter 11
1 Basics on SRAM Testing 12
1.1 Overview of Semiconductor Memories 12
1.2 Typical Structure of an SRAM 14
1.3 The Context of SRAM Testing 16
1.3.1 Memory Model 17
1.3.2 Fault Model Representation 18
1.3.3 Fault Model Classification 19
1.3.4 Test Solutions and Algorithms 23
1.4 Test Generation 26
1.5 Test Validation 28
1.6 Conclusion 30
2 Resistive-Open Defects in Core-Cells 31
2.1 The SRAM Core-Cell 31
2.1.1 Reading in the Core-Cell 31
2.1.2 Writing in the Core-Cell 32
2.2 Analysis of Resistive-Open Defects in the Core-Cell 33
2.2.1 Defect Location 33
2.2.2 Defect Incidence Analysis 33
2.2.3 Simulation Set-Up and Results 36
2.3 Analysis and Test of dRDF 37
2.3.1 Functional Fault Modeling of dRDF 38
2.3.2 RES: Read Equivalent Stress 39
2.3.3 March Test Solutions Detecting dRDFs 43
2.4 Analysis and Test of dDRF 47
2.4.1 Functional Fault Modeling of dDRF 47
2.4.2 Experiments 48
2.4.2.1 dDRF Due to Defect Df4 50
2.4.2.2 dDRF Due to Defects Df2 and Df3 52
2.4.3 March Test Solution Detecting dDRFs 53
2.5 Impact of Technology Scaling 55
2.6 Conclusion 58
3 Resistive-Open Defects in Pre-charge Circuits 59
3.1 The SRAM Pre-charge Circuit 59
3.2 Analysis of Resistive-Open Defects in the Pre-charge Circuit 61
3.2.1 Defect Location 61
3.2.2 Defect Incidence Analysis 62
3.2.3 Simulation Set-Up and Results 63
3.3 Analysis and Test of URRF and URWF 64
3.3.1 Functional Fault Modeling of URRF and URWF 64
3.3.2 Experiments 65
3.3.3 March Test Solutions Detecting URWFs 70
3.4 Conclusion 74
4 Resistive-Open Defects in Address Decoders 75
4.1 The SRAM Address Decoder 75
4.2 Analysis of Resistive-Open Defects in the Address Decoder 77
4.3 Analysis and Test of ADOF 77
4.3.1 Functional Fault Modeling of ADOF 78
4.3.2 Experiments 80
4.3.2.1 Timing Constraints 83
4.3.3 March Test Solution Detecting ADOFs 85
4.3.3.1 Sachdev's Algorithm Converted in March Elements 87
4.3.3.2 March iC- 89
4.4 Conclusion 90
5 Resistive-Open Defects in Write Drivers 91
5.1 The SRAM Write Driver 91
5.1.1 Write Driver Within the I/O Circuitry 91
5.1.2 Operation Mode of the Write Driver 92
5.2 Analysis of Resistive-Open Defects in the Write Driver 94
5.2.1 Defect Location 94
5.2.2 Defect Incidence Analysis 95
5.2.3 Simulation Set-Up and Results 96
5.3 Analysis and Test of SWDF 97
5.3.1 Functional Fault Modeling of SWDF 97
5.3.2 Experiments 98
5.3.2.1 SWDF Due to Df5 98
5.3.2.2 SWDF Due to Df6 99
5.3.3 March Test Solution Detecting SWDFs 100
5.4 Analysis and Test of URWF/URDWF 102
5.4.1 Functional Fault Modeling of URDWF 102
5.4.2 Experiments 103
5.4.2.1 URDWF Due to Df9 103
5.4.2.2 URDWF vs. URWF 105
5.4.3 March Test Solution Detecting URDWFs 106
5.5 Conclusion 106
6 Resistive-Open Defects in Sense Amplifiers 108
6.1 The SRAM Sense Amplifier 108
6.1.1 Sense Amplifier Within the I/O Circuitry 108
6.1.2 Operation Mode of the Sense Amplifier 108
6.2 Analysis of Resistive-Open Defects in the Sense Amplifier 111
6.2.1 Defect Location 112
6.2.2 Defect Incidence Analysis 112
6.2.3 Simulation Set-Up and Results 113
6.3 Analysis and Test of d2cIRF1 114
6.3.1 Functional Fault Modeling of d2cIRF1 114
6.3.2 Experiments 115
6.3.3 March Test Solution Detecting d2cIRF1s 116
6.4 Analysis and Test of d2cIRF2 119
6.4.1 Functional Fault Modeling of d2cIRF2 119
6.4.2 Experiments 120
6.4.3 March Test Solution Detecting d2cIRF2s 121
6.5 d2cIRF1 vs. d2cIRF2 122
6.6 Conclusion 123
7 Faults Due to Process Variations in SRAMs 124
7.1 Influence of Threshold Voltage Deviations in SRAM Core-Cells 124
7.1.1 Simulation Flow 125
7.1.2 Mismatch Sensitivity During Read/Write Operations 125
7.1.3 V t Mismatch Related Fault Models 128
7.1.3.1 Result Overview 129
7.1.3.2 Test Requirements 130
7.2 Impact of Leakage Current of Core-Cell Pass-Transistors on the Read Operation 130
7.2.1 Analysis of Supply Voltage Variations 136
7.2.2 Analysis of Temperature Variations 137
7.2.3 Test and Diagnosis of LRFs 137
7.3 Complex Read Fault Analysis 139
7.4 Conclusion 141
8 Diagnosis and Design-for-Diagnosis 142
8.1 Diagnosis Methods 142
8.1.1 Cause--Effect Approach: Signature-Based Diagnosis 142
8.1.1.1 Principle 142
8.1.1.2 Extension to Dynamic Fault Diagnosis 143
8.1.2 Effect--Cause Approach: History-Based Diagnosis 146
8.1.2.1 Principle 147
8.1.2.2 Extension to Dynamic Fault Diagnosis 150
8.1.2.3 Experimental Results 156
8.2 Design-for-Diagnosis of Write Drivers 159
8.2.1 Requirements for Fault-Free Operations of a Write Driver 159
8.2.2 Description of the Current-Based DfD Solution 161
8.2.3 Description of the Voltage-Based DfD Solution 163
8.2.4 Diagnosis Sequence 166
8.3 Conclusion 167
Summary 168
References 171
Index 176