FPGA Design (eBook)

Phil Simpson is Altera’s senior manager for software technical marketing and product planning. In this role, Simpson is responsible for Altera’s Quartus II software and third-party EDA interfaces product planning and the creation of the Altera design flow software roadmap. Prior to joining Altera in 1996, Simpson held several engineering roles at various EDA and semiconductor companies, including EDA Solutions, Data I/O and Lucas Aerospace. Simpson holds a BS (with honors) in Electrical & Electronic Engineering from City University, London and an MSC (with distinction) in system design from the University of Central England, Birmingham, England.

Preface 6
Contents 8
List of Figures 14
Chapter 1: Best Practices for Successful FPGA Design 18
1.1 Introduction 18
Chapter 2: Project Management 21
2.1 The Role of Project Management 21
2.1.1 Project Management Phases 21
2.1.2 Estimating a Project Duration 22
2.1.3 Schedule 22
2.1.3.1 Weekly Schedule Analysis 22
2.1.3.2 Pro-active Project Management 23
Chapter 3: Design Specification 24
3.1 Design Specification: Communication Is Key to Success 24
3.1.1 High Level Functional Specification 24
3.1.2 Functional Design Specification 25
3.1.2.1 Functional Specification Outline 26
3.1.2.2 Test Specification Outline 27
Chapter 4: Resource Scoping 29
4.1 Introduction 29
4.2 Engineering Resources 29
4.3 Third Party IP 30
4.4 Device Selection 30
4.4.1 Silicon Specialty Features 31
4.4.2 Density 32
4.4.3 Speed Requirements 33
4.4.4 Pin-Out 33
4.4.5 Power 34
4.4.6 Availability of IP 34
4.4.7 Availability of Silicon 34
4.4.8 Summary 35
Chapter 5: Design Environment 36
5.1 Introduction 36
5.2 Scripting Environment 36
5.3 Interaction with Version Control Software 37
5.4 Use of a Problem Tracking System 38
5.5 A Regression Test System 39
5.6 When to Upgrade the Versions of the FPGA Design Tools 39
5.7 Common Tools in the FPGA Design Environment 40
Chapter 6: Board Design 42
6.1 Challenges that FPGAs Create for Board Design 42
6.2 Engineering Roles and Responsibilities 43
6.2.1 FPGA Engineers 43
6.2.2 PCB Design Engineer 44
6.2.3 Signal Integrity Engineer 45
6.3 Power and Thermal Considerations 46
6.3.1 Filtering Power Supply Noise 46
6.3.2 Power Distribution 46
6.4 Signal Integrity 47
6.4.1 Types of Signal Integrity Problems 47
6.4.1.1 Signal Integrity on One Net 47
6.4.1.2 Crosstalk 48
6.4.1.3 Rail Collapse 48
6.4.2 Electromagnetic Interference 48
6.5 Design Flows for Creating the FPGA Pinout 49
6.5.1 User Flow 1: FPGA Designer Driven 49
6.5.2 User Flow 2 51
6.5.3 How Do FPGA and Board Engineers Communicate Pin Changes? 53
6.6 Board Design Check List for a Successful FPGA Pin-Out 53
Chapter 7: Power and Thermal Analysis 54
7.1 Introduction 54
7.2 Power Basics 55
7.2.1 Static Power 55
7.2.2 Dynamic Power 55
7.2.3 I/O power 55
7.2.4 Inrush Current 56
7.2.5 Configuration Power 56
7.3 Key Factors in Accurate Power Estimation 56
7.3.1 Accurate Power Models of the FPGA Circuitry 57
7.3.2 Accurate Toggle Rate Data on Each Signal 57
7.3.3 Accurate Operating Conditions 58
7.3.4 Resource Utilization 59
7.4 Power Estimation Early in the Design Cycle(Power Supply Planning) 59
7.5 Simulation Based Power Estimation(Design Power Verification) 60
7.5.1 Partial Simulations 63
7.6 Best Practices for Power Estimation 63
Chapter 8: RTL Design 64
8.1 Introduction 64
8.2 Common Terms and Terminology 64
8.3 Recommendations for Engineers with an ASIC Design Background 66
8.4 Recommended FPGA Design Guidelines 67
8.4.1 Synchronous Versus Asynchronous 67
8.4.2 Global Signals 67
8.4.2.1 Clock Network Resources 68
8.4.3 Dedicated Hardware Blocks 68
8.4.3.1 Instantiation Versus Inferencing 69
8.4.4 Use of Low-Level Design Primitives 69
8.4.5 Managing Metastability 70
8.5 Writing Effective HDL 70
8.5.1 What’s the Best Language 71
8.5.1.1 Mixed Language Design 71
8.5.2 Good Design Practices 72
8.5.2.1 Documented Code 72
8.5.2.2 Recommended Signal Naming Convention 73
8.5.2.3 Hierarchy and Design Partitioning 73
8.5.2.4 Design Reuse 76
8.5.2.5 Techniques for Reducing Design Cycle Time 76
8.5.2.6 Design for Debug 77
8.5.3 HDL for Synthesis 78
8.5.3.1 Coding Styles 78
8.5.3.2 General Verilog Guidelines 79
8.5.3.3 General VHDL Guidelines 79
8.5.3.4 Designing for Performance 79
Timing Margin 80
8.5.3.5 Designing for Area 81
8.5.3.6 Synthesis Tool Settings 81
8.5.3.7 Inferencing of FPGA Design Blocks 82
RAMs 82
Read During Write Behavior 82
ROMs 83
Finite State Machines 83
State Machine Encoding Styles 84
Safe State Machines 85
Large Complex State Machines 85
DSP Blocks 85
Registers 86
Secondary Signals for Registers 86
Conditional Statements 87
8.6 Analyzing the RTL Design 88
8.6.1 Synthesis Reports 88
8.6.1.1 Source Files 88
8.6.1.2 Synthesis Settings 88
8.6.1.3 Resource Usage Information 88
8.6.1.4 State Machines 89
8.6.1.5 Optimization Information 89
8.6.1.6 Timing Estimates 89
8.6.2 Messages 89
8.6.3 Block Diagram View 90
8.7 Recommended Best Practices for RTL Design 91
Chapter 9: IP and Design Reuse 92
9.1 Introduction 92
9.2 The Need for IP Reuse 92
9.2.1 Benefits of IP Reuse 93
9.2.2 Challenges in Developing a Design Reuse Methodology 93
9.2.2.1 Engineers Mindset 93
9.2.2.2 Awareness of Reusable Design Blocks 94
9.2.2.3 Development Effort 94
9.3 Make Versus Buy 95
9.4 Architecting Reusable IP 96
9.4.1 Specification 96
9.4.2 Implementation Methods 96
9.4.2.1 Parameterized RTL 96
9.4.2.2 High Level Synthesis 97
9.4.2.3 IP Generator 98
9.4.3 Use of Standard Interfaces 98
9.5 Packaging of IP 99
9.5.1 Documentation 100
9.5.2 User Interface 100
9.5.3 Compatibility with System Integration Tools 101
9.5.4 IP Security 102
9.6 IP Reuse Checklist 103
Chapter 10: The Hardware to Software Interface 104
10.1 Software Interface 104
10.2 Definition of Register Address Map 104
10.3 Use of the Register Address Map 104
10.3.1 IP Selection 105
10.3.2 Software Engineers Interface 105
10.3.3 RTL Engineers Interface 105
10.3.4 Verification Interface 106
10.3.5 Documentation 106
10.4 Summary 107
Chapter 11: Functional Verification 108
11.1 Introduction 108
11.2 Challenges of Functional Verification 108
11.3 Glossary of Verification Concepts 109
11.4 RTL Versus Gate Level Simulation 110
11.5 Verification Methodology 110
11.6 Attack Complexity 111
11.6.1 Modularize Your Design and Your Tests 111
11.6.2 Plan for Expected Operation 111
11.6.3 Plan for the Unexpected 111
11.7 Functional Coverage 112
11.7.1 Directed Testing 113
11.7.2 Random Dynamic Simulation 113
11.7.3 Constrained Random Tests 113
11.7.4 Use of System Verilog for Design and Verification 113
11.7.4.1 Assertions 114
11.7.5 General Testbench Methods 114
11.7.6 Self Verifying Testbenches 115
11.7.7 Formal Equivalency Checking 116
11.8 Code Coverage 117
11.9 QA Testing 117
11.9.1 Functional Regression Testing 117
11.9.2 GUI Testing for Reusable IP 118
11.10 Hardware Interoperability Tests 118
11.11 Hardware/Software Co-Verification 119
11.11.1 Getting to Silicon Fast 119
11.12 Functional Verification Checklist 119
Chapter 12: Timing Closure 120
12.1 Timing Closure Challenges 120
12.2 The Importance of Timing Assignments and Timing Analysis 121
12.2.1 Background 121
12.2.2 Basics of Timing Analysis 122
12.2.2.1 Static Timing Analysis 122
12.2.2.2 SDC 122
12.2.2.3 Clocks 122
12.2.2.4 Launch Edge 123
12.2.2.5 Latch Edge 123
12.2.2.6 Hold Time (th) 123
12.2.2.7 Set-Up Time (tsu) 123
12.2.2.8 Arrival Time 124
12.2.2.9 Required Time 124
12.2.2.10 Slack 125
12.2.2.11 Timing Exception 125
12.2.2.12 Multi-Cycle Path 125
12.2.2.13 False Path 125
12.2.2.14 Source Synchronous 126
12.2.2.15 Rise/Fall Time 126
12.2.2.16 Input Delay 126
12.2.2.17 Output Delay 126
12.2.2.18 Operating Conditions 127
12.2.2.19 Multi-corner Analysis 127
12.2.2.20 Slow Corner Model 127
12.2.2.21 Fast Corner Model 127
12.2.2.22 Clock Uncertainty 127
12.2.2.23 Clock Latency 128
12.3 A Methodology for Successful Timing Closure 128
12.3.1 Family and Device Assignments 128
12.3.1.1 Speed-Grade Selection 128
12.3.1.2 I/O Settings 129
12.3.2 Design Planning 129
12.3.2.1 Incremental Compilation 130
Top-Down Design Flow 131
Bottom-Up Design Flow 131
12.3.2.2 Design Scenarios Using Incremental Compilation 132
Scenario 1: Parameter Tuning 133
Scenario 2: Bug Fixing 133
Scenario 3: Timing Closure 134
12.3.3 Early Timing Estimation 134
12.3.4 CAD Tool Settings 135
12.3.4.1 Understanding the Fitter (Place and Route) 135
12.3.4.2 Advanced Optimization: When You Need More 136
Physical Synthesis Optimizations 136
Design Space Exploration 137
12.3.4.3 Compilation Reports and Analysis Tools 137
12.3.4.4 Floorplanning Tools 139
Architecture Exploration 141
Analysis of Placement and Routing 141
Floorplan Assignments 141
Engineering Change Orders 142
12.4 Common Timing Closure Issues 142
12.4.1 Missing Timing Constraints 143
12.4.2 Conflicting Timing Constraints 143
12.4.3 High Fan-Out Registers 143
12.4.4 Missing Timing by a Small Margin 144
12.4.5 Restrictive Location Constraints 144
12.4.6 Long Compile Times 144
12.5 Design Planning, Implementation, Optimizationand Timing Closure Checklist 145
Chapter 13: In-System Debug 146
13.1 In-System Debug Challenges 146
13.2 Planning 147
13.3 Techniques 147
13.3.1 Use of Pins for Debug 147
13.3.2 Internal Logic Analyzer 148
13.3.2.1 The Design Flow with an ILA 150
13.3.2.2 ILA Limitations 150
13.3.2.3 Tips 150
Remote Debug 150
Interface to MATLAB 151
Insufficient Device Resources 151
13.3.3 Use of Debug Logic 151
13.3.4 External Logic Analyzer 152
13.3.5 Editing Memory Contents 152
13.3.6 Use of a Soft Processor for Debug 153
13.4 Use Scenarios 153
13.4.1 Power-Up Debug 153
13.4.2 Debug of Transceiver Interfaces 154
13.4.3 Reporting of System Performance 154
13.4.4 Debug of Soft Processors 155
13.4.4.1 Software Profiling 155
13.4.4.2 Watchpoints 156
13.4.4.3 Stack Overflow 156
13.4.4.4 Breakpoints 156
13.4.4.5 Step Through the Code 156
13.4.5 Device Programming Issues 156
13.5 In-System Debug Checklist 157
Chapter 14: Design Sign-Off 158
14.1 Sign-Off Process 158
14.2 After Sign-Off 158
Bibliography 160
Index 161