Power-efficient System Design (eBook)
X, 253 Seiten
Springer US (Verlag)
978-1-4419-6388-8 (ISBN)
The Information and communication technology (ICT) industry is said to account for 2% of the worldwide carbon emissions - a fraction that continues to grow with the relentless push for more and more sophisticated computing equipment, c- munications infrastructure, and mobile devices. While computers evolved in the directionofhigherandhigherperformanceformostofthelatterhalfofthe20thc- tury, the late 1990's and early 2000'ssaw a new emergingfundamentalconcern that has begun to shape our day-to-day thinking in system design - power dissipation. As we elaborate in Chapter 1, a variety of factors colluded to raise power-ef?ciency as a ?rst class design concern in the designer's mind, with profound consequences all over the ?eld: semiconductor process design, circuit design, design automation tools, system and application software, all the way to large data centers. Power-ef?cient System Design originated from a desire to capture and highlight the exciting developments in the rapidly evolving ?eld of power and energy op- mization in electronic and computer based systems. Tremendous progress has been made in the last two decades, and the topic continues to be a fascinating research area. To develop a clearer focus, we have concentrated on the relatively higher level of design abstraction that is loosely called the system level. In addition to the ext- sive coverage of traditional power reduction targets such as CPU and memory, the book is distinguished by detailed coverage of relatively modern power optimization ideas focussing on components such as compilers, operating systems, servers, data centers, and graphics processors.
Preface 6
Contents 8
1 Low Power Design: An Introduction 12
1.1 The Emergence of Power as an Important Design Metric 12
1.2 Power Efficiency vs. Energy Efficiency 14
1.3 Power-Performance Tradeoff 17
1.4 Power Density 18
1.5 Power and Energy Benchmarks 18
1.6 Power Optimizations at the System Level 18
1.7 Organization of this Book 20
References 21
2 Basic Low Power Digital Design 22
2.1 CMOS Transistor Power Consumption 22
2.1.1 Switching Power 24
2.1.2 Short Circuit Power 25
2.1.3 Leakage Power 26
2.1.3.1 Reverse Biased Diode Leakage 26
2.1.3.2 Gate Induced Drain Leakage 26
2.1.3.3 Gate Oxide Tunneling 27
2.1.3.4 Subthreshold Leakage 28
2.2 Trends in Power Consumption 29
2.3 Techniques for Reducing Dynamic Power 29
2.3.1 Gate Sizing 31
2.3.2 Control Synthesis 34
2.3.3 Clock Gating 36
2.3.4 Voltage and Frequency Scaling 39
2.3.4.1 Design-Time Voltage and Frequency Setting 40
2.3.4.2 Static Voltage and Frequency Scaling 40
2.3.4.3 Dynamic Voltage and Frequency Scaling 41
2.4 Techniques for Reducing Short Circuit Power 41
2.5 Techniques for Reducing Leakage Power 42
2.5.1 Multiple Supply Voltage 42
2.5.2 Multiple Threshold Voltage 44
2.5.3 Adaptive Body Biasing 45
2.5.4 Transistor Stacking 45
2.5.5 Power Gating 47
2.6 Summary 48
References 49
3 Power-efficient Processor Architecture 52
3.1 Introduction 52
3.1.1 Power Budget: A Major Design Constraint 56
3.1.1.1 Why does Parallel Processing Reduce Power? 56
3.1.2 Processor Datapath Architecture 59
3.1.2.1 Instruction Fetch 60
3.1.2.2 Decode and Dispatch 61
3.1.2.3 Issue 62
3.1.2.4 Execute 62
3.1.2.5 Commit 63
3.1.3 Power Dissipation 63
3.2 Front-end: Fetch and Decode Logic 65
3.2.1 Fetch Gating 65
3.2.1.1 Branch Confidence Estimation 66
3.2.1.2 Rate Mismatch Flow Control 68
3.2.2 Auxiliary Decode Buffer 69
3.3 Issue Queue / Dispatch Buffer 71
3.3.1 Dynamic Adaptation of Issue Queue Size 74
3.3.2 Zero Byte Encoding 75
3.3.3 Banking and Bit-line Segmentation 76
3.3.4 Fast Comparators 77
3.4 Register File 77
3.4.1 Port Reduction and Banking 78
3.4.1.1 Reducing Port Requirements 78
3.4.1.2 Banking 80
3.4.2 Clustered Organization 81
3.4.3 Hierarchical Organization 81
3.5 Execution Units 83
3.5.1 Clock Gating 84
3.5.2 Operand Isolation/Selective Evaluation 84
3.5.3 Power Gating and Multi-threshold Logic 85
3.5.3.1 Time Based 86
3.5.3.2 Branch Prediction Based 87
3.5.3.3 Compiler Based 88
3.6 Reorder Buffer 88
3.6.1 Port Reduction 90
3.6.2 Distributed ROB 91
3.6.3 Dynamic ROB Sizing 92
3.6.4 Zero Bytes and Power Efficient Comparators 92
3.7 Branch Prediction Unit 92
3.7.1 Banking of BHT and BTB 95
3.7.2 Reducing BHT/BTB Lookups 95
3.8 Summary 96
References 97
4 Power-efficient Memory and Cache 100
4.1 Introduction and Memory Structure 101
4.1.1 Overview 101
4.1.2 Memory Structure 102
4.1.3 Cache Memory 103
4.1.4 Cache Architecture 109
4.1.5 Power Dissipation During Memory Access 111
4.2 Power-efficient Memory Architectures 112
4.2.1 Partitioned Memory and Caches 112
4.2.2 Augmenting with Additional Memories 114
4.2.3 Reducing Tag and Data Array Fetches 116
4.2.4 Reducing Cache Leakage Power 120
4.3 Translation Look-aside Buffer (TLB) 122
4.3.1 TLB Associativity – A Power-performance Trade-off 124
4.3.2 Banking 124
4.3.3 Reducing TLB Lookups 126
4.3.3.1 Deferred Address Translation 126
4.3.3.2 Using Address Mapping Register 126
4.4 Scratch Pad Memory 127
4.4.1 Data Placement in SPM 128
4.4.2 Dynamic Management of SPM 130
4.4.3 Storing both Instructions and Data in SPM 132
4.5 Memory Banking 132
4.6 Memory Customization 135
4.7 Reducing Address Bus Switching 140
4.7.1 Encoding 140
4.7.2 Data Layout 142
4.8 DRAM Power Optimization 145
4.9 Summary 146
References 147
5 Power Aware Operating Systems, Compilers, and ApplicationSoftware 150
5.1 Operating System Optimizations 151
5.1.1 Advanced Configuration and Power Interface (ACPI) 155
5.1.1.1 Power Modes 157
5.1.2 Dynamic Voltage and Frequency Scaling 159
5.1.2.1 DVFS in Real-time OS 162
5.1.3 I/O Device Power Management 171
5.2 Compiler Optimizations 172
5.2.1 Loop Transformations 173
5.2.2 Instruction Encoding 173
5.2.3 Instruction Scheduling 175
5.2.4 Dual Instruction Set Architectures 175
5.2.5 Instruction Set Extension 179
5.2.6 Power Gating 182
5.2.7 Dynamic Translation and Recompilation 183
5.2.8 Compiler Optimizations Targeting Disks 184
5.3 Application Software 185
5.3.1 Application-aided Power Management 185
5.3.2 DVFS Under Application Control 186
5.3.2.1 MPEG Video Decoder 186
5.3.2.2 Word Processor 187
5.3.2.3 Batch Compilation 188
5.3.3 Output Quality Trade-offs 188
5.4 Summary 189
References 189
6 Power Issues in Servers and Data Centers 194
6.1 Power Efficiency Challenges 194
6.1.1 Nameplate Power Overestimates Actual Power 195
6.1.2 Installed vs. Utilized Capacity 196
6.1.3 Load Variation 196
6.2 Where does the Power go? 197
6.3 Server Power Modeling and Measurement 199
6.4 Server Power Management 201
6.4.1 Frequency Scaling 201
6.4.2 Processor and Memory Packing 204
6.4.3 Power Shifting 207
6.5 Cluster and Data Center Power Management 208
6.5.1 Power Capping/Thresholding 209
6.5.2 Voltage and Frequency Scaling 212
6.6 Summary 215
References 215
7 Low Power Graphics Processors 218
7.1 Introduction to Graphics Processing 219
7.1.1 Graphics Pipeline 219
7.1.1.1 Application Stage 219
7.1.1.2 Geometry 221
7.1.1.3 Triangle Setup 223
7.1.1.4 Rasterization 224
7.1.1.5 Display 226
7.1.2 Graphics Processor Architecture 227
7.1.3 Power Dissipation in a Graphics Processor 232
7.2 Programmable Units 233
7.2.1 Clock Gating 234
7.2.2 Predictive Shutdown 234
7.2.3 Code Transformation 235
7.3 Texture Unit 239
7.3.1 Custom Memory Architecture – Texture Filter Memory 240
7.3.2 Texture Compression 243
7.3.3 Clock Gating 245
7.4 Raster Operations 246
7.4.1 Depth Buffer Compression 246
7.4.2 Color Buffer Compression 248
7.5 System Level Power Management 249
7.5.1 Power Modes 249
7.5.2 Dynamic Voltage and Frequency Scaling 249
7.5.2.1 History based Workload Estimation 252
7.5.2.2 Control Theory based Workload Estimation 252
7.5.2.3 Frame Structure based Workload Estimation 254
7.5.2.4 Signature based Workload Estimation 255
7.5.3 Multiple Power Domains 256
7.6 Summary 256
References 257
Index 260
| Erscheint lt. Verlag | 23.7.2010 |
|---|---|
| Zusatzinfo | X, 253 p. |
| Verlagsort | New York |
| Sprache | englisch |
| Themenwelt | Informatik ► Weitere Themen ► CAD-Programme |
| Technik ► Elektrotechnik / Energietechnik | |
| Technik ► Nachrichtentechnik | |
| Schlagworte | Architecture • Circuit Design • Computer-Aided Design (CAD) • Digital Design • Low Power Design • Low Power Digital Design • Low Power Embedded System Design • Low Power Graphics Processor • Low Power Processor Architecture • Low Power System Design • Power Aware C • Power Aware Code • Power Aware Load Balencing • Power Eff • Power Efficient Design |
| ISBN-10 | 1-4419-6388-X / 144196388X |
| ISBN-13 | 978-1-4419-6388-8 / 9781441963888 |
| Haben Sie eine Frage zum Produkt? |
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