Timing Optimization Through Clock Skew Scheduling (eBook)
XVI, 266 Seiten
Springer US (Verlag)
978-0-387-71056-3 (ISBN)
This book details timing analysis and optimization techniques for circuits with level-sensitive memory elements. It contains a linear programming formulation applicable to the timing analysis of large scale circuits and includes a delay insertion methodology that improves the efficiency of clock skew scheduling. Coverage also provides a framework for and results from implementing timing optimization algorithms in a parallel computing environment.
History of the Book The last three decades have witnessed an explosive development in - tegrated circuit fabrication technologies. The complexities of current CMOS circuits are reaching beyond the 65 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the succe- ful design and implementation of thousands of high performance, large scale integrated circuits. This book (a research monograph) originated from a body of doctoral d- sertationresearchcompletedbythe?rstauthorattheUniversityofRochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution network in large scale, high performance digital synchronous circuits and particularly, on algorithmsfornon-zero clockskewscheduling.Duringthedevelopmentofthis research, it became clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical developments in this area have been slow to reach the designers' desktops. The second edition of the book is enhanced by the body of doctoral dissertation research completed by the second author at the University of Pittsburgh from 2000 to 2005 under the supervision of Prof.
Preface 5
Contents 8
List of Figures 12
1 Introduction 16
2 VLSI Systems 22
3 Signal Delay in VLSI Systems 34
4 Timing Properties of Synchronous Systems 55
5 Clock Skew Scheduling and Clock Tree Synthesis 85
6 Clock Skew Scheduling of Level-Sensitive Circuits 111
7 Clock Skew Scheduling for Improved Reliability 135
8 Delay Insertion and Clock Skew Scheduling 158
9 Practical Considerations 179
10 Clock Skew Scheduling in Rotary Clocking Technology 194
11 Experimental Results 216
12 Conclusions 253
References 257
Index 268
Erscheint lt. Verlag | 16.11.2008 |
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Zusatzinfo | XVI, 266 p. |
Verlagsort | New York |
Sprache | englisch |
Themenwelt | Informatik ► Weitere Themen ► CAD-Programme |
Technik ► Elektrotechnik / Energietechnik | |
Schlagworte | algorithms • Automation • Circuit Timing • Clock Skew Scheduling • Clock Timing • Computer • EDA • Integrated circuit • microprocessor • Optimization • Placement Methodologies • programming • Signal • VLSI • VLSI CAD |
ISBN-10 | 0-387-71056-6 / 0387710566 |
ISBN-13 | 978-0-387-71056-3 / 9780387710563 |
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