Clocking in Modern VLSI Systems (eBook)

Clocking in Modern VLSI Systems 4
Preface 7
Contents 9
List of Figures 15
List of Tables 22
List of Contributors 23
1 Introduction and Overview 24
1.1 The Clock Design Problem 25
1.2 Some Subjective Milestones in the Historyof Microprocessor Clocking 27
1.2.1 Integrating the PLL 27
1.2.2 Clock Distribution Moves to the Forefront: The Dawn of the GHz Race 27
1.2.3 Delay Lock Techniques 28
1.2.4 Exploiting Inductance for Oscillation and Distribution 28
1.2.5 Variable Frequency (and Voltage) 28
1.2.6 Frequency Increase (or Supply Lowering) Through Resiliency 29
1.3 Overview of this Book 29
References 30
2 Modern Clock Distribution Systems 32
2.1 Introduction 32
2.2 Definitions and Design Requirements 33
2.2.1 Setup and Hold Timing Constraints 34
2.2.2 Clock Attributes 36
Static and Dynamic Clock Uncertainties 37
Distribution Delay 42
Duty Cycle 42
2.2.3 Clock Distribution Power 42
2.3 Clock Distribution Topologies 44
2.3.1 Unconstrained Tree 44
2.3.2 Balanced Tree 46
2.3.3 Central Spine 48
2.3.4 Spines with Matched Branches 48
2.3.5 Grid 49
2.3.6 Hybrid Distribution 52
2.4 Microprocessor Clock Distributions 53
2.5 Clock Design for Test and Manufacturing 59
2.5.1 Global and Local Clock Compensations 59
2.5.2 Global Clock Compensation Architecture 60
2.5.3 Local Clock Compensation Architecture 66
2.6 Elements of Clock Distribution Circuits 67
2.6.1 Clock Duty Cycle 67
2.6.2 Power Supply 70
2.7 Clock DFX Techniques 71
2.7.1 Optical Probing 71
2.7.2 On-Die Measurement 72
2.7.3 Locating Critical Path 75
2.7.4 On-Die-Clock Shrink 75
2.8 Multiclock Domain Distributions 77
2.8.1 Multicore Processor Clock Distribution 78
2.9 Future Directions 81
2.10 Conclusion 81
References 82
3 Clocked Elements 89
3.1 Introduction 89
3.2 CSE Design Issues 90
3.2.1 Latency 90
3.2.2 Hold Time 91
3.2.3 Power 92
3.2.4 Scan Design for CSEs 93
3.3 Static Latch Designs 94
3.3.1 Master--Slave Latches 94
3.3.2 Two-Phase Level-Sensitive Latches 98
3.3.3 Pulsed-Clock Static Level-Sensitive Latches 100
3.4 Flip-Flop Designs 102
3.4.1 Sense-Amp Style Flip-Flop 102
3.4.2 Hybrid Latch Flip-Flop 104
3.4.3 Semi-Dynamic Flip-Flop 105
3.5 Test and Debug Considerations 107
3.6 CSE Design for Variability 110
3.6.1 Variability-Induced Frequency Degradation 110
3.6.2 Variability-Induced Functional Failures 111
3.7 Reliability Issues 113
3.7.1 Soft Error Rate Considerations 113
3.7.2 End of Life Considerations for CSE Design 115
3.8 Conclusion 118
Acknowledgments 118
References 119
4 Exploiting Inductance 126
4.1 Introduction 126
4.2 Monolithic Inductance 127
4.2.1 Spiral Inductors 127
4.2.2 Transmission Lines 131
4.3 Inductor-Based Clock Generation 136
4.3.1 Differential LC VCO 136
4.3.2 Quadrature LC VCO 139
4.3.3 Distributed VCO 141
4.3.4 Poly-Phase Circularly Distributed VCO 142
4.4 Clock Distribution Using Inductance 144
4.4.1 Rotary Traveling-Wave Oscillator Arrays 144
4.4.2 Standing Wave Oscillator and Grid 145
4.4.3 Inductor-Based Resonant Global Clock Distribution 149
4.5 Conclusion 152
Acknowledgments 152
References 153
5 Phase Noise and Jitter 159
5.1 Introduction 159
5.2 Timing Error in the Time Domain: Jitter 160
5.2.1 Phase Jitter 161
5.2.2 Period Jitter 161
5.2.3 Cycle-to-Cycle Jitter 162
5.3 Timing Error in the Frequency Domain: Phase Noise 162
5.3.1 Relationship Between Phase Noise and Jitter 163
5.4 Frequency Domain Modeling of PLLs 164
5.4.1 PLL Phase Noise 164
5.4.2 PLL Intrinsic Noise: VCO 165
5.4.3 PLL Intrinsic Noise: Feedback Divider 166
5.4.4 PLL Intrinsic Noise: Phase Detector 166
5.4.5 PLL Intrinsic Noise: Charge Pump 168
5.4.6 PLL Intrinsic Noise: Loop Filter 170
5.4.7 PLL Extrinsic Noise: Reference Clock 171
5.4.8 PLL Extrinsic Noise: Supply Noise 172
5.4.9 PLL Extrinsic Noise: Buffer Delay and Noise 172
5.4.10 PLL Phase Noise Filtering 173
Some Intuition on Reference Clock Phase Noise(or Jitter) Filtering 175
5.4.11 Phase Noise to Period Jitter and Phase Noise to C2C Jitter 176
5.4.12 Phase, Period, and C2C Jitter Examples 179
Phase Jitter 179
Period Jitter 180
C2C Jitter 180
5.5 Reference Clock Jitter Transfer Example: Microprocessor 181
5.5.1 A Proposed Core Clock Methodology Using Mean Time Between Failures (MTBF) 181
5.6 Non-Random Jitter Distributions 186
5.6.1 Reference Spurs in PLLs 187
5.6.2 Duty Cycle Distortion (DCD) 189
5.6.3 Power Supply Noise 190
5.6.4 Inter-Symbol Interference (ISI) 191
5.6.5 Including Deterministic Jitter in Analysis 192
5.7 Reference Clock Jitter Transfer Example: Serial Link 193
5.7.1 Serial Link Budgeting 193
5.7.2 Bit Error Rate 194
5.7.3 Serial Link Block Diagram 194
5.8 Delay Locked Loops (DLLs) and Jitter 198
5.9 Conclusion 199
Acknowledgements 199
References 200
6 Digital Delay Lock Techniques 202
6.1 Introduction 202
6.2 What Constitutes a Digital Delay Locked Loop? 202
6.3 An Overview of DLL Applications 205
6.4 Phase Detectors 206
6.4.1 Metastability 210
An Example of Phase Detector Failure Calculation 220
6.5 DCDL Design 221
6.5.1 Gate-Delay DCDLs 222
Synchronous vs. Asynchronous Operation in Coarse DCDLs 226
6.5.2 Subgate-Delay DCDLs 228
6.5.3 Resolution vs. Dynamic Range in DCDLs 230
6.6 Control 235
6.6.1 Sensitivity to Initial Phase 236
6.6.2 Dynamic Range Increase 238
6.6.3 Stability and Bandwidth 238
6.6.4 Lock Acquisition 245
6.7 Putting it All Together 248
6.8 Noise Considerations 248
6.9 Advanced Applications 255
6.9.1 Duty Cycle Correction 255
6.9.2 Clock Multiplication 255
6.9.3 Infinite Dynamic Range 257
6.9.4 Clock-Data Recovery 258
6.9.5 On-Chip Temperature Sensing 260
6.10 Conclusion 261
Acknowledgments 261
References 261
7 Clocking and Variation 264
7.1 Introduction 264
7.2 Variation Reduction Through Design 264
7.2.1 Skew and Jitter-Tolerant Design 265
7.2.2 Time Borrowing for Datapath Variation Reduction 265
7.3 Variation Reduction Through Tuning 270
7.3.1 Manufacturing Techniques 271
7.3.2 Active Clock Deskew 271
7.3.3 Dynamic Frequency 274
7.4 Variation Reduction Through Resiliency 280
7.4.1 Timing Error Detection -- Error Detection Sequentials 281
7.4.2 Timing Error Correction and Recovery 285
7.4.3 Results: Guardband Reduction Through Resiliency 287
7.5 Conclusion 291
Acknowledgments 292
References 292
8 Physical Design Considerations 294
8.1 Introduction 294
8.2 Clock Skew Components 295
8.2.1 Setup Time Skew 300
8.2.2 Hold Time Skew 302
8.2.3 Half-Cycle Setup Skew 302
8.2.4 Multiple-Cycle Setup Skew 302
8.2.5 Grid or H-Tree? 302
8.3 Transistor Variation 303
8.3.1 Channel Length Variation 303
Photolithography Challenges 305
Poly Flaring and Poly Pullback 306
Line Edge Roughness 307
Channel Length Variation Control 307
8.3.2 Dopant Fluctuation 309
8.3.3 Well Proximity Effect 310
8.3.4 Strain 311
Stress Memorization and Tensile Stress Liner 312
SiGe and Compressive Stress Liner 312
Shallow Trench Isolation 314
New Materials 315
Guidelines 315
8.3.5 Long Term Effects on Variation 315
NBTI 315
Hot Carrier Injection 317
8.4 Voltage Variation 317
8.5 Temperature Variation 319
8.6 Interconnect Variation 320
8.7 Conclusion: Clock Design and Analysis Guidelines:Putting All Together 326
8.7.1 Clock Analysis 326
8.7.2 Minimizing Variation 326
Acknowledgments 327
References 327
Index 336