Languages for Embedded Systems and their Applications (eBook)

Preface 6
Contents 8
Model-Based System Specification Languages 16
Power and Energy Estimations in Model-Based Design 17
Introduction 17
AADL Component Based Design Flow 19
Consumption Analysis: the Methodology 21
Power Estimation 22
Power Models 23
Multi-level Estimation 25
Refinement Level 1 25
Refinement Level 2 26
Refinement Level 3 28
Power Estimation for Complex DSP 28
Power Estimation for Field Programmable Gate Array 30
Power Estimation for Operating System Services 31
Ethernet Communications Consumption Modelling 32
Analysis of Relevant Parameters 32
Power and Energy Characterisation 32
Models 33
Consumption Analysis Tool 34
Property Sets 34
Conclusion 37
References 38
MARTE vs. AADL for Discrete-Event and Discrete-Time Domains 41
Introduction 41
Marte Time Model 42
Definitions 43
Event-Triggered Communications 43
Time-Triggered Communications 44
Periodic Tasks and Physical Time 45
TimeSquare 45
AADL 45
Modeling Elements 45
AADL Application Software Components 46
AADL Flows 47
AADL Ports 47
Three Different Configurations 48
The Aperiodic Case 48
The Mixed Event-Data Flow Case 51
The Periodic Case 52
Conclusion 53
Glossary 54
References 54
Generation of MARTE Allocation Models from Activity Threads 56
Introduction 56
Related Work 58
Building System Models with MARTE 59
Utilizing Activity Threads for Design-Space Exploration 60
Generating MARTE Allocation Models with Activity Threads 61
A Prototypic Implementation of the Method 64
Visualization of Performance Feedback 66
Summary and Outlook 67
References 68
Model-Driven System Validation by Scenarios 70
Introduction 70
ASMs and ASMETA 72
Scenario-Based Validation of ASM Models 73
The AValLa Language 73
The Model-Driven Validation Environment 74
From SystemC UML Models to ASM Models 75
Model Validator 77
The Simple Bus Case Study 77
Related Work 79
Conclusions and Future Work 81
References 81
An Advanced Simulink Verification Flow Using SystemC 83
Introduction 83
Related Work 84
Extended Verification Flow 85
Conventional Flow 85
Conventional Test Bench Concept 86
Extended Test Bench Concept 87
Extending the Verification Flow 88
Implementation 89
Synchronization 89
Data Type Conversion 92
Evaluation 92
Implementation 92
Extended Verification Flow 94
Conclusion 95
References 96
Languages for Heterogeneous System Design 97
VHDL-AMS Implementation of a Numerical Ballistic CNT Model 98
Introduction 98
Mobile Charge Density and Self-Consistent Voltage 99
Numerical Piece-Wise Approximation of the Charge Density 100
Performance of Numerical Approximations 102
VHDL-AMS Implementation 104
Conclusion 109
Acknowledgements 110
References 110
Wide-Band Sigma-Delta ADC Design in Superconducting Technology 112
Introduction 112
Sigma-Delta Second Order Architecture 113
Bandpass Sigma-Delta Modulator 113
The Josephson Junction 114
The RSFQ Balanced Comparator 116
Sigma Delta Modulator Operation with Josephson Junctions 116
System Modeling with VHDL-AMS 117
The Sigma-Delta ADC Design 118
Clock and Comparator Design 118
Simulation Results 120
Conclusion 122
References 123
Heterogeneous and Non-linear Modeling in SystemC-AMS 124
Introduction 124
SystemC-AMS Modeling Platform 125
Summary of Electrostatic Harvester Operation 127
Resonant Electromechanical Transducer 127
Conditioning Circuit Operation 128
SystemC-AMS Modeling of the Harvester 129
Resonator Modeling 129
Implementation of the Conditioning Circuit Model 130
Variable Capacitor 130
Diode Implementation 130
Initial Charge of the Capacitors 133
Conditioning Circuit/Flyback Switch Modeling 134
Modeling of the Diode D3 134
Model of the Whole System 134
Modeling Results 135
Description of the Modeling Experiment 135
Modeling Results Validation 137
Conclusion 138
References 138
Digital Systems Design Methodologies Based on C++ 140
Application Workload and SystemC Platform Modeling for Performance Evaluation 141
Introduction 141
Performance Modeling and Simulation 143
Application and Workload Modeling 143
Execution Platform Modeling 144
Component Layer 145
Subsystem Layer 145
Platform Architecture Layer 145
Interfaces 146
Allocation and Transformation to SystemC 147
Performance Simulation 148
Mobile Video Player Case Example 148
Modeling of the Execution Platform Components 149
Modeling of the Services 151
Modeling of the Application 153
Analysis of Simulation Results 154
Conclusions 155
Acknowledgements 156
References 156
Adaptive Interconnect Models for Transaction-Level Simulation 158
Introduction 158
Related Work 160
Adaptive Interconnect Models 161
Point-to-Point Communication 161
Bus-Based Communication 163
Model Implementation 166
An Adaptive FSL Model 166
An Adaptive AHB Model 167
Experimental Results 169
Conclusion 173
References 173
Efficient Architecture Evaluation Using Functional Mapping 175
Introduction 175
Functional Mapping 176
Timing Behavior 177
Conventional Code Transformation 177
Optimization Approach 179
Class Unitized 179
Customize and Apply Unitized 181
Application of u_trace 182
Using the Approach in the Design Flow 183
Handling Arrays 183
Design Example 184
Simulation Results 186
Limitations and Experiences 187
Summary 189
Outlook 189
References 189
Symbolic Scheduling of SystemC Dataflow Designs 191
Introduction 191
Model of Computation 192
Symbolic Representation 195
QSS of SysteMoC Models 197
Transition Graphs 198
Path Searching 199
Scheduling Algorithm 201
Related Work 203
Example 204
Conclusions and Further Work 205
References 206
SystemC Simulation of Networked Embedded Systems 208
Introduction 208
The Architecture of SCNSL 210
Main Components of SCNSL 211
Main Problems Solved by SCNSL 214
Simulation of RTL Models 214
Assessment of Transmission Validity 214
Simulation Planning 215
Application to a Wireless Scenario 215
Experimental Results 217
Conclusions 217
References 218
Modeling of Embedded Software Multitasking in SystemC/OSSS 219
Introduction 219
Related Work 220
The OSSS Design Flow 222
Application Layer 222
Virtual Target Architecture Layer 223
Modeling Software in OSSS 224
Abstraction of Run-time System 224
Software Tasks 225
Software Shared Objects 226
Software Execution Times 227
Exploration of Platform Effects 228
Simulation Results 229
Accuracy and Performance 229
Lazy Synchronization 230
Conclusion 231
References 231
High-Level Reconfiguration Modeling in SystemC 233
Introduction 233
Related Work 234
Basic Reconfiguration Modeling 235
Interpreting Reconfiguration as Circuit Switch 235
Creating Reconfigurable Modules from Static Ones 236
Control 237
Advanced ReChannel Features 237
Exportals 237
Synchronization 238
Explicit Description of Reconfiguration 239
Resettable Processes 240
Resettable Components 242
Binding Groups of Switches 243
Case Study 244
Conclusion and Future Work 245
References 246
Stream Programming for FPGAs 247
Introduction 247
Stream Computing 249
Streaming on FPGAs 250
Compiling Brook to Hardware 250
Example Brook Program 252
Exploiting Data Parallelism 254
Experimental Evaluation 256
Results 257
Concluding Remarks 258
References 259
Verification and Requirements Evaluation 260
A New Verification Technique for Custom-Designed Components at the Arithmetic Bit Level 261
Introduction 261
Normalization Method 263
ABL Normalization 263
Merging of Addition Networks 265
Distribution of Partial Products 266
Mixed ABL/Gate-Level Problems 266
Synthesis of ABL Descriptions from Gate-Level Models 267
Generation of the Equivalent ABL Descriptions for Boolean Functions in Reed-Muller Form 268
Experimental Results 272
Conclusion and Future Work 275
References 276
Debugging Contradictory Constraints in Constraint-Based Random Simulation 277
Introduction 277
SystemC Verification Library 279
Contradiction Analysis 280
Problem Formulation 280
Concepts for Contradiction Analysis 281
Implementation 284
Experimental Evaluation 286
Types of Contradictions 287
Effect of Property 1 and Property 2 288
Real-Life Example 289
Conclusions 292
References 293
Design of Communication Infrastructures for Reconfigurable Systems 295
Introduction 295
Related Works 297
Real World Applications Analysis 297
Applications Layer 298
Scenarios Layer 299
Characteristics Layer 299
Metrics Layer 300
The Proposed Solution 301
High Level Description 302
High Level Network Simulation 303
Evaluation and Selection 305
Verification and Validation 306
Results 306
Concluding Remarks 310
References 310
Analysis of Non-functional Properties of MPSoC Designs 312
Introduction 312
Related Work 314
Preliminaries 315
Activity Model 315
Power Management Model 316
Design Flow 316
Abstraction of System Functionality 317
Simulation Model Generation 318
Communication Dependency Graphs 318
Temporal Environment Models 319
Integration of Power Consumption and Power Management 321
Battery Models, Placement and Chip Environment 322
Experimental Results 323
Conclusions 325
References 326