Designing Reliable and Efficient Networks on Chips (eBook)

Dr. Srinivasan Murali is a co-founder and CTO of iNoCs and a research scientist at the Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland. He received the MS and PhD degrees in Electrical Engineering from Stanford University in 2007. His research interests include interconnect design for Systems on Chips, with particular emphasis on developing CAD tools and design methods for Networks on Chips. His interests also include thermal modeling and reliability of multi-core systems. He has been actively involved in several conferences (such as DATE, CODES-ISSS, NoC symposium, VLSI-SoC) as a program committee member/session chair and is a reviewer for many leading conferences and journals. He is a recipient of the EDAA outstanding dissertation award for 2007 for his work on interconnect architecture design.  He received a best paper award at the DATE 2005 conference and a best paper nomination at the ICCAD 2006 conference.  One of his papers has also been selected as one of "The Most Influential Papers of 10 Years DATE". He has over 30 publications in leading conferences and journals in this field.

Preface 6
Contents 8
Introduction 12
Networks on Chips: Scalable Interconnects for SoCs 12
NoC Design Challenges 15
Book Overview 16
NoC Design Methods 16
NoC Reliability Mechanisms 18
Related Work 18
NoC Architectures and Design Methods 19
Reliability Support for NoCs 21
NoC Design Methods 24
Designing Crossbar Based Systems 25
Problem Motivation and Application Traffic Analysis 27
Problem Motivation 27
Application Traffic Analysis 29
Design Methodology 29
Exact Approach to Crossbar Synthesis 32
Problem Formulation 32
Exact Crossbar Synthesis Algorithm 34
Heuristic Approach to Crossbar Synthesis 34
Experiments and Case Studies 38
Experimental Platform and Power Models 38
Application Benchmark Analysis 39
Comparisons of Heuristic Engine with the Exact Engine 42
Window Sizing 44
Real-Time Streams & Effect of Binding
Overlap Threshold Setting 46
Summary 47
Netchip Tool Flow for NoC Design 48
Front-End Design Phase 48
Architectural Design Phase: The xpipes NoC Library 49
Summary 51
Designing Standard Topologies 52
On-Chip Traffic Modeling 54
Problem Formulation 56
Mapping and Physical Planning Algorithm 59
Physical Planning 60
Experiments and Case Studies 62
Effect of Physical Planning 62
Design for QoS Guarantees 62
VOPD Design 63
Buffer Sizing and Network Optimization 63
Summary 65
Designing Custom Topologies 66
Objectives 66
Background on NoC Topology Synthesis 67
Background on Deadlock-Free NoC Design 68
Input Models 69
Area, Power Models 69
Traffic Models 71
Design Algorithms 71
Experiments and Case Studies 77
Experiments on MPSoC Benchmarks 77
Layout-Level Comparisons 79
Impact of Frequency Constraints 81
Handling Dynamic Effects 83
Summary 83
Supporting Multiple Applications 85
The Æthereal NoC Architecture 86
Switch/NI Architecture 87
Dynamic NoC Reconfiguration 87
Design Methodology 88
Use-Case Preprocessing 90
Unified Mapping-NoC Configuration 91
Simulation Results 97
Experimental Benchmarks 97
Effect of Mapping for SoC Benchmarks 98
Frequency-Area Trade-offs 99
Dynamic Configuration 100
Parallel Use-Cases 101
Summary 101
Supporting Dynamic Application Patterns 102
NoC Design Challenges for CMPs 102
Basics of the Synthesis Approach 104
Design Flow 105
Problem Formulation 106
Synthesis Algorithm 108
NoC Link Sizing 109
Timing Feasibility Check 112
Algorithm Run-Time 112
Experimental Results 112
Experiments on a Mesh Topology 113
Effect of Core Injection Rates 114
Effect of Different NoC Sizes 115
Effect of Link Length 117
Application to Torus Topology 117
Validating Design Flow Predictability 118
Summary 119
NoC Reliability Mechanisms 121
Timing-Error Tolerant NoC Design 122
The Double Sampling Technique 123
Using Links as a Storage Medium 125
T-error Link Designs 128
Scheme 1: Low overhead T-error Links 128
Scheme 2: High-Performance T-error Links 131
Aggressive Switch/NI Design 133
Output Buffer Changes 133
Input Buffer Changes 134
Dynamic Configuration of the NoC 135
Experimental Results 136
Simulation Platform 136
Experiments on a Multi-Media Benchmark 136
Effect of Application-Level Power Management 139
Experiments on Other Benchmarks 139
Effect of NoC Configuration 143
Choice of Link Design Schemes 143
Synthesis Results 144
Summary 144
Analysis of NoC Error Recovery Schemes 145
Switch Architecture Design 146
End-to-End Error Detection 146
Switch-to-Switch Error Detection 147
Hybrid Single Error Correcting, Multiple Error Detecting Scheme 147
Energy Estimation and Models 148
Energy Estimation 148
Error Models 148
Experiments and Simulation Results 148
Power Consumption of Schemes for Fixed Residual Error Rates 148
Performance Comparison of Reliability Schemes 150
Power Consumption Overhead of Reliability Schemes 150
Effect of Buffering Requirements, Traffic Patterns and Packet Size 153
Summary 155
Fault-Tolerant Route Generation 157
Multi-Path Routing with In-Order Delivery 159
Path Selection Algorithm 160
Multipath Traffic Splitting 164
Fault-Tolerance Support with Multipath Routing 165
Resilience Against Transient Errors 165
Resilience Against Permanent Errors 166
Simulation Results 168
Area, Power and Timing Overhead 168
Case Study: MPEG Decoder 168
Comparisons with Single-Path Routing 169
Effect of Fault-Tolerance Support 170
Summary 171
NoC Support for Reliable On-Chip Memories 172
Analysis of Multimedia Software 173
Baseline SoC Architecture and Extensions 175
SoC Template Architecture 175
Proposed Hardware Extensions 176
Run-Time Fault Tolerant Schemes 179
Permanent Error Recovery Support 180
Intermittent Error Recovery Support 181
Experimental Results 181
Performance Studies 182
Architectural Exploration of NoC Features 185
Effects of Varying Percentages of Critical Data 186
Synthesis Results 187
Summary 189
Conclusions and Future Directions 190
Putting It All Together 190
Bibliography 193
Journal Publications 198
Conference Publications 199