On-Line Testing for VLSI

Michael Nicolaidis, Yervant Zorian, Dhiraj Pradhan (Herausgeber)

Buch | Softcover

160 Seiten

2010 | Softcover reprint of hardcover 1st ed. 1998
Springer-Verlag New York Inc.
978-1-4419-5033-8 (ISBN)

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Test functions (fault detection, diagnosis, error correction, repair, etc.) that are applied concurrently while the system continues its intended function are defined as on-line testing. In its expanded scope, on-line testing includes the design of concurrent error checking subsystems that can be themselves self-checking, fail-safe systems that continue to function correctly even after an error occurs, reliability monitoring, and self-test and fault-tolerant designs.
On-Line Testing for VLSI contains a selected set of articles that discuss many of the modern aspects of on-line testing as faced today. The contributions are largely derived from recent IEEE International On-Line Testing Workshops. Guest editors Michael Nicolaidis, Yervant Zorian and Dhiraj Pradhan organized the articles into six chapters. In the first chapter the editors introduce a large number of approaches with an expanded bibliography in which some references date back to the sixties.
On-Line Testing for VLSI is an edited volume of original research comprising invited contributions by leading researchers.

1: Introduction.- 1.1. On-Line Testing for VLSI—A Compendium of Approaches.- 2: Self-Checking Design.- 2.1. On-Line Fault Monitoring.- 2.2. Efficient Totally Self-Checking Shifter Design.- 2.3. A New Design Method for Self-Checking Unidirectional Combinational Circuits.- 2.4. Concurrent Delay Testing in Totally Self-Checking Systems.- 3: Self Checking Checkers.- 3.1. Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters.- 3.2. Self-Testing Embedded Two-Rail Checkers.- 4: On-Line Monitoring of Reliability Indicators.- 4.1. Thermal Monitoring of Self-Checking Systems.- 4.2. Integrated Temperature Sensors for On-Line Thermal Monitoring of Microelectronics Structures.- 4.3. Clocked Dosimeter Compatible with Digital CMOS Technology.- 5: Built-In Self-Test.- 5.1. Scalable Test Generators for High-Speed Datapath Circuits.- 5.2. Mixed-Mode BIST Using Embedded Processors.- 5.3. A BIST Scheme for Non-Volatile Memories.- 6: Fault Tolerant Systems.- 6.1. On-Line Fault Resilience Through Gracefully Degradable ASICs.- 6.2. Delivering Dependable Telecommunication Services Using Off-the-Shelf System Components.

Erscheint lt. Verlag	6.12.2010
Reihe/Serie	Frontiers in Electronic Testing ; 11
Zusatzinfo	IV, 160 p.
Verlagsort	New York, NY
Sprache	englisch
Maße	178 x 254 mm
Themenwelt	Informatik ► Weitere Themen ► CAD-Programme
Themenwelt	Technik ► Elektrotechnik / Energietechnik
ISBN-10	1-4419-5033-8 / 1441950338
ISBN-13	978-1-4419-5033-8 / 9781441950338
Zustand	Neuware