Digital Electronics and Design with VHDL (eBook)

Digital Electronics and Design with VHDL 4
Copyright Page 5
Contents 8
Preface 20
Chapter 1. Introduction 24
1.1 Historical Notes 24
1.2 Analog versus Digital 27
1.3 Bits, Bytes, and Words 28
1.4 Digital Circuits 29
1.5 Combinational Circuits versus Sequential Circuits 33
1.6 Integrated Circuits 33
1.7 Printed Circuit Boards 34
1.8 Logic Values versus Physical Values 36
1.9 Nonprogrammable, Programmable, and Hardware Programmable 38
1.10 Binary Waveforms 38
1.11 DC, AC, and Transient Responses 39
1.12 Programmable Logic Devices 41
1.13 Circuit Synthesis and Simulation with VHDL 42
1.14 Circuit Simulation with SPICE 42
1.15 Gate-Level versus Transistor-Level Analysis 43
Chapter 2. Binary Representations 44
2.1 Binary Code 44
2.2 Octal and Hexadecimal Codes 47
2.3 Gray Code 47
2.4 BCD Code 48
2.5 Codes for Negative Numbers 49
2.6 Floating-Point Representation 53
2.7 ASCII Code 58
2.8 Unicode 59
2.9 Exercises 63
Chapter 3. Binary Arithmetic 70
3.1 Unsigned Addition 70
3.2 Signed Addition and Subtraction 72
3.3 Shift Operations 75
3.4 Unsigned Multiplication 77
3.5 Signed Multiplication 79
3.6 Unsigned Division 80
3.7 Signed Division 81
3.8 Floating-Point Addition and Subtraction 82
3.9 Floating-Point Multiplication 84
3.10 Floating-Point Division 85
3.11 Exercises 86
Chapter 4. Introduction to Digital Circuits 92
4.1 Introduction to MOS Transistors 92
4.2 Inverter and CMOS Logic 94
4.3 AND and NAND Gates 100
4.4 OR and NOR Gates 102
4.5 XOR and XNOR Gates 104
4.6 Modulo-2 Adder 106
4.7 Buffer 107
4.8 Tri-State Buffer 108
4.9 Open-Drain Buffer 109
4.10 D-Type Flip-Flop 110
4.11 Shift Register 112
4.12 Counters 114
4.13 Pseudo-Random Sequence Generator 116
4.14 Exercises 117
Chapter 5. Boolean Algebra 126
5.1 Boolean Algebra 126
5.2 Truth Tables 131
5.3 Minterms and SOP Equations 131
5.4 Maxterms and POS Equations 133
5.5 Standard Circuits for SOP and POS Equations 135
5.6 Karnaugh Maps 140
5.7 Large Karnaugh Maps 143
5.8 Other Function-Simplification Techniques 144
5.9 Propagation Delay and Glitches 146
5.10 Exercises 148
Chapter 6. Line Codes 156
6.1 The Use of Line Codes 156
6.2 Parameters and Types of Line Codes 158
6.3 Unipolar Codes 160
6.4 Polar Codes 161
6.5 Bipolar Codes 162
6.6 Biphase/Manchester Codes 162
6.7 MLT Codes 163
6.8 mB/nB Codes 163
6.9 PAM Codes 166
6.10 Exercises 171
Chapter 7. Error-Detecting/Correcting Codes 176
7.1 Codes for Error Detection and Error Correction 176
7.2 Single Parity Check (SPC) Codes 177
7.3 Cyclic Redundancy Check (CRC) Codes 178
7.4 Hamming Codes 179
7.5 Reed-Solomon (RS) Codes 182
7.6 Interleaving 184
7.7 Convolutional Codes 186
7.8 Viterbi Decoder 190
7.9 Turbo Codes 193
7.10 Low Density Parity Check (LDPC) Codes 194
7.11 Exercises 197
Chapter 8. Bipolar Transistor 204
8.1 Semiconductors 204
8.2 The Bipolar Junction Transistor 206
8.3 I-V Characteristics 207
8.4 DC Response 208
8.5 Transient Response 212
8.6 AC Response 214
8.7 Modern BJTs 215
8.8 Exercises 217
Chapter 9. MOS Transistor 220
9.1 Semiconductors 220
9.2 The Field-Effect Transistor (MOSFET) 221
9.3 I-V Characteristics 224
9.4 DC Response 225
9.5 CMOS Inverter 228
9.6 Transient Response 230
9.7 AC Response 232
9.8 Modern MOSFETs 233
9.9 Exercises 235
Chapter 10. Logic Families and I/Os 242
10.1 BJT-Based Logic Families 242
10.2 Diode-Transistor Logic 243
10.3 Transistor-Transistor Logic (TTL) 244
10.4 Emitter-Coupled Logic 248
10.5 MOS-Based Logic Families 249
10.6 CMOS Logic 250
10.7 Other Static MOS Architectures 253
10.8 Dynamic MOS Architectures 255
10.9 Modern I/O Standards 258
10.10 Exercises 271
Chapter 11. Combinational Logic Circuits 280
11.1 Combinational versus Sequential Logic 280
11.2 Logical versus Arithmetic Circuits 281
11.3 Fundamental Logic Gates 281
11.4 Compound Gates 282
11.5 Encoders and Decoders 285
11.6 Multiplexer 291
11.7 Parity Detector 295
11.8 Priority Encoder 295
11.9 Binary Sorter 297
11.10 Shifters 298
11.11 Nonoverlapping Clock Generators 300
11.12 Short-Pulse Generators 301
11.13 Schmitt Triggers 302
11.14 Memories 303
11.15 Exercises 304
11.16 Exercises with VHDL 310
11.17 Exercises with SPICE 310
Chapter 12. Combinational Arithmetic Circuits 312
12.1 Arithmetic versus Logic Circuits 312
12.2 Basic Adders 313
12.3 Fast Adders 316
12.4 Bit-Serial Adder 323
12.5 Signed Adders/Subtracters 324
12.6 Incrementer, Decrementer, and Two’s Complementer 326
12.7 Comparators 327
12.8 Arithmetic-Logic Unit 329
12.9 Multipliers 330
12.10 Dividers 335
12.11 Exercises 335
12.12 Exercises with VHDL 340
12.13 Exercises with SPICE 340
Chapter 13. Registers 342
13.1 Sequential versus Combinational Logic 342
13.2 SR Latch 343
13.3 D Latch 343
13.4 D Flip-Flop 352
13.5 Master-Slave D Flip-Flops 355
13.6 Pulse-Based D Flip-Flops 361
13.7 Dual-Edge D Flip-Flops 365
13.8 Statistically Low-Power D Flip-Flops 366
13.9 D Flip-Flop Control Ports 367
13.10 T Flip-Flop 368
13.11 Exercises 370
13.12 Exercises with SPICE 375
Chapter 14. Sequential Circuits 376
14.1 Shift Registers 376
14.2 Synchronous Counters 378
14.3 Asynchronous Counters 391
14.4 Signal Generators 394
14.5 Frequency Dividers 397
14.6 PLL and Prescalers 400
14.7 Pseudo-Random Sequence Generators 404
14.8 Scramblers and Descramblers 406
14.9 Exercises 409
14.10 Exercises with VHDL 418
14.11 Exercises with SPICE 418
Chapter 15. Finite State Machines 420
15.1 Finite State Machine Model 420
15.2 Design of Finite State Machines 422
15.3 System Resolution and Glitches 433
15.4 Design of Large Finite State Machines 434
15.5 Design of Finite State Machines with Complex Combinational Logic 437
15.6 Multi-Machine Designs 440
15.7 Generic Signal Generator Design Technique 442
15.8 Design of Symmetric-Phase Frequency Dividers 444
15.9 Finite State Machine Encoding Styles 446
15.10 Exercises 449
15.11 Exercises with VHDL 455
Chapter 16. Volatile Memories 456
16.1 Memory Types 456
16.2 Static Random Access Memory (SRAM) 457
16.3 Dual and Quad Data Rate (DDR, QDR) SRAMs 461
16.4 Dynamic Random Access Memory (DRAM) 462
16.5 Synchronous DRAM (SDRAM) 465
16.6 Dual Data Rate (DDR, DDR2, DDR3) SDRAMs 467
16.7 Content-Addressable Memory (CAM) for Cache Memories 469
16.8 Exercises 470
Chapter 17. Nonvolatile Memories 474
17.1 Memory Types 474
17.2 Mask-Programmed ROM (MP-ROM) 475
17.3 One-Time-Programmable ROM (OTP-ROM) 476
17.4 Electrically Programmable ROM (EPROM) 476
17.5 Electrically Erasable Programmable ROM (EEPROM) 478
17.6 Flash Memory 479
17.7 Next-Generation Nonvolatile Memories 484
17.8 Exercises 488
Chapter 18. Programmable Logic Devices 490
18.1 The Concept of Programmable Logic Devices 490
18.2 SPLDs 491
18.3 CPLDs 494
18.4 FPGAs 501
18.5 Exercises 509
Chapter 19. VHDL Summary 514
19.1 About VHDL 515
19.2 Code Structure 515
19.3 Fundamental VHDL Packages 518
19.4 Predefined Data Types 519
19.5 User Defined Data Types 521
19.6 Operators 521
19.7 Attributes 523
19.8 Concurrent versus Sequential Code 524
19.9 Concurrent Code (WHEN, GENERATE) 525
19.10 Sequential Code (IF, CASE, LOOP, WAIT) 526
19.11 Objects (CONSTANT, SIGNAL, VARIABLE) 529
19.12 Packages 532
19.13 Components 533
19.14 Functions 536
19.15 Procedures 537
19.16 VHDL Template for FSMs 539
19.17 Exercises 543
Chapter 20. VHDL Design of Combinational Logic Circuits 546
20.1 Generic Address Decoder 546
20.2 BCD-to-SSD Conversion Function 548
20.3 Generic Multiplexer 550
20.4 Generic Priority Encoder 552
20.5 Design of ROM Memory 553
20.6 Design of Synchronous RAM Memories 555
20.7 Exercises 559
Chapter 21. VHDL Design of Combinational Arithmetic Circuits 562
21.1 Carry-Ripple Adder 562
21.2 Carry-Lookahead Adder 563
21.3 Signed and Unsigned Adders/Subtracters 566
21.4 Signed and Unsigned Multipliers/Dividers 568
21.5 ALU 570
21.6 Exercises 573
Chapter 22. VHDL Design of Sequential Circuits 576
22.1 Shift Register with Load 576
22.2 Switch Debouncer 579
22.3 Timer 581
22.4 Fibonacci Series Generator 584
22.5 Frequency Meters 585
22.6 Neural Networks 588
22.7 Exercises 594
Chapter 23. VHDL Design of State Machines 596
23.1 String Detector 596
23.2 “Universal” Signal Generator 598
23.3 Car Alarm 601
23.4 LCD Driver 611
23.5 Exercises 620
Chapter 24. Simulation with VHDL Testbenches 624
24.1 Synthesis versus Simulation 624
24.2 Testbench Types 625
24.3 Stimulus Generation 626
24.4 Testing the Stimuli 628
24.5 Testbench Template 630
24.6 Writing Type I Testbenches 630
24.7 Writing Type II Testbenches 635
24.8 Writing Type III Testbenches 638
24.9 Writing Type IV Testbenches 638
24.10 Exercises 641
Chapter 25. Simulation with SPICE 644
25.1 About SPICE 644
25.2 Types of Analysis 645
25.3 Basic Structure of SPICE Code 646
25.4 Declarations of Electronic Devices 648
25.5 Declarations of Independent DC Sources 653
25.6 Declarations of Independent AC Sources 654
25.7 Declarations of Dependent Sources 658
25.8 SPICE Inputs and Outputs 659
25.9 DC Response Examples 661
25.10 Transient Response Examples 664
25.11 AC Response Example 667
25.12 Monte Carlo Analysis 668
25.13 Subcircuits 671
25.14 Exercises Involving Combinational Logic Circuits 673
25.15 Exercises Involving Combinational Arithmetic Circuits 675
25.16 Exercises Involving Registers 677
25.17 Exercises Involving Sequential Circuits 678
Appendix A. ModelSim Tutorial 680
Appendix B. PSpice Tutorial 690
References 696
Index 702