Demystifying Chipmaking (eBook)

Cover 1
Contents 5
Foreword 11
Acknowledgments 13
About the Authors 15
Chapter 1: IC Fabrication Overview 19
Section 1: Introduction 21
1.1 Integrated Circuits 21
1.2 The Semiconductor Industry 24
Section 2: Support Technologies 25
2.1 Crystal Growth and Wafer Preparation 25
2.2 Contamination Control 26
2.3 Circuit Design and Mask Making 28
2.4 Process Diagnostics and Metrology 30
Section 3: Integrated Circuit Fabrication 31
3.1 Layering 31
3.2 Patterning 36
3.3 Doping 39
3.4 Process Control and In-line Monitoring 40
Section 4: Test and Assembly 43
4.1 Electrical Tests 43
4.2 Die Separation 43
4.3 Die Attach and Wire Bonding 43
4.4 Encapsulation 44
4.5 Final Test 44
Section 5: Summary 45
Chapter 2: Support Technologies 47
Section 1: Introduction 49
Section 2: Contamination Control 51
2.1 Why Control Contamination? 51
2.2 Contamination Sources 53
2.3 The Cleanroom 54
Section 3: Crystal Growth and Wafer Preparation 59
3.1 Introduction 59
3.2 Silicon Purification 60
3.3 Czochralski Silicon Growth 61
3.4 Shaping, Grinding, Cutting and Polishing 64
3.5 Final Inspection and Shipping 65
Section 4: Circuit Design 67
4.1 Introduction 67
4.2 Product Definition and New Product Plan 68
4.3 The Design Team 71
4.4 The Design Process 73
4.5 Design Verification and Tapeout 75
Section 5: Photomask and Reticle Preparation 77
5.1 Introduction 77
5.2 Reticle Substrate Preparation 77
5.3 Pattern Transfer 78
5.4 Inspection and Defect Repair 79
Chapter 3: Forming Wells 81
Section 1: Introduction 83
Section 2: Initial Oxidation 89
Section 3: Photolithography 97
3.1 Introduction 97
3.2 Coat (Spin) 100
3.3 Exposure (Step) 101
3.4 Develop 102
3.5 After Develop Inspect (ADI) 103
Section 4: Ion Implantation 105
Chapter 4: Isolate Active Areas (Shallow Trench Isolation) 111
Section 1: Introduction to Shallow Trench Isolation 113
Section 2: Pad Oxide Growth 117
Section 3: Silicon Nitride Deposition 119
Section 4: Photolithography for Photo/Etch 123
Section 5: Hard Mask Formation Using Plasma Etch 125
5.1 Hard Mask Overview 125
5.2 Plasma Etch Overview 127
5.3 Etch Chemistry: Silicon Dioxide and Silicon Nitride 132
Section 6: Form Trenches in Silicon with Plasma Etch 137
Section 7: Fill Trenches with Silicon Dioxide 139
Section 8: Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide 141
Section 9: Wet Etch Removal of Silicon Nitride and Pad Oxide 145
Chapter 5: Building the Transistors 147
Section 1: Introduction 149
Section 2: Thin Film Formation 155
2.1 Gate Dielectric Oxidation 155
2.2 Polycrystalline Silicon (Poly) Deposition 158
2.3 Nitride Cap Deposition 160
Section 3: Poly Gate Formation 161
3.1 Photoresist Patterning 161
3.2 Plasma Etch 162
Section 4: Source/Drain Formation 165
4.1 Introduction 165
4.2 Shallow Implant 167
4.3 Spacer Formation 167
4.4 High-Dose Implant 169
4.5 Anneal 169
Section 5: Salicide Formation 171
5.1 Sputter Cobalt 173
5.2 RTP Reaction Forming Silicide 173
5.3 Strip Residual Cobalt 174
5.4 Anneal the Silicide 174
Chapter 6: First Level Metallization 175
Section 1: Introduction 177
Section 2: Nitride and Oxide Depositions 181
2.1 Nitride Deposition 181
2.2 Oxide Deposition 182
Section 3: CMP Planarization 185
Section 4: Photo/Etch for Contact Holes 187
4.1 Contact Hole Photolithography 187
4.2 Contact Etch 188
Section 5: Tungsten Plug Process 191
5.1 Deposit Ti/TiN Barrier/Glue Layers 191
5.2 Tungsten CVD 192
5.3 Tungsten CMP 194
Section 6: Low-k Dielectric Process 195
6.1 Deposit Low-k Dielectric Film 195
6.2 Trench Photolithography and Etch 198
Section 7: Copper First Level Interconnection Process 201
7.1 Ta/TaN Barrier Layer Deposition 201
7.2 Sputter Copper (Cu) 203
7.3 Electroplate Copper (Cu) 203
7.4 Copper CMP 204
Chapter 7: Multilevel Metal Interconnects and Dual Damascene 207
Section 1: Introduction 209
Section 2: Deposit Barrier Layer and Intermetal Dielectric 213
Section 3: Dual Damascene Process 215
3.1 Introduction 215
3.2 Via Photo/Etch 216
3.3 Trench Photo/Etch 217
3.4 Deposit Barrier Layers 218
3.5 Sputter Copper 218
3.6 Electroplate Copper 218
3.7 CMP to Remove Excess Copper 219
3.8 Deposit SiC Barrier Layer 220
3.9 Build Additional Layers 220
Section 4: Form Bonding Pads 221
Section 5: Final Passivation Process 223
5.1 Deposit Final Passivation 223
5.2 Photo/Etch for Bonding Pads 223
Chapter 8: Test and Assembly 225
Section 1: Introduction 227
Section 2: Wafer and Chip Testing 229
2.1 In-line Parametric Test 229
2.2 Wafer Sort (Probe) 230
2.3 Final Functional Test 231
Section 3: Assembly and Packaging 233
3.1 Die Separation 233
3.2 Die Attach and Bond Pad Connection 234
3.3 Encapsulation 236
Appendix A: Science Overview 237
Introduction 239
Section 1: Atoms and Molecules 241
1.1 The Atom 241
1.2 Molecules 244
1.3 Organic Molecules 245
Section 2: Gases 247
2.1 Facts about Gases 247
2.2 Ions 248
2.3 Plasma 248
2.4 Free Radicals 249
2.5 Excited States 249
Section 3: Chemistry 251
3.1 Introduction 251
3.2 Thin Film Deposition Chemistry 251
3.3 Plasma Etch Chemistry 253
Section 4: Solids 255
4.1 Conductors and Insulators 255
4.2 Semiconductors 256
4.3 pn Junctions 257
Section 5: Electricity, Electric and Magnetic Fields 259
5.1 Electric Charges and Fields 259
5.2 Electric Current 260
5.3 Magnetic Field 261
Appendix B: Plasma Etch Supplement to Chapter 4 263
Section 1: Plasma Etcher Theory 265
Section 2: Plasma Etch Process Requirements 267
Bibliography 269
Index 271