Memory Systems (eBook)

Front Cover 1
In Praise of Memory Systems: Cache, DRAM, Disk 2
Memory Systems Cache, DRAM, Disk 6
Copyright Page 7
Contents 10
Preface 32
Overview. On Memory Systems and Their Design 36
Ov.1 Memory Systems 37
Ov.2 Four Anecdotes on Modular Design 49
Ov.3 Cross-Cutting Issues 55
Ov.4 An Example Holistic Analysis 76
Ov.5 What to Expect 89
Part I. Cache 90
Chapter 1. An Overview of Cache Principles 92
1.1 Caches, ‘Caches,’ and “Caches” 94
1.2 Locality Principles 97
1.3 What to Cache, Where to Put It, and How to Maintain It 101
1.4 Insights and Optimizations 108
Chapter 2. Logical Organization 114
2.1 Logical Organization: A Taxonomy 114
2.2 Transparently Addressed Caches 117
2.3 Non-Transparently Addressed Caches 125
2.4 Virtual Addressing and Protection 127
2.5 Distributed and Partitioned Caches 132
2.6 Case Studies 138
Chapter 3. Management of Cache Contents 152
3.1 Case Studies: On-Line Heuristics 155
3.2 Case Studies: Off-Line Heuristics 186
3.3 Case Studies: Combined Approaches 204
3.4 Discussions 237
3.5 Building a Content-Management 247
Chapter 4. Management of Cache Consistency 252
4.1 Consistency with Backing Store 253
4.2 Consistency with Self 255
4.3 Consistency with Other Clients 261
Chapter 5. Implementation Issues 292
5.1 Overview 292
5.2 SRAM Implementation 293
5.3 Advanced SRAM Topics 328
5.4 Cache Implementation 332
Chapter 6. Cache Case Studies 336
6.1 Logical Organization 336
6.2 Pipeline Interface 339
6.3 Case Studies of Detailed Itanium-2 Circuits 340
Part II. DRAM 348
Chapter 7. Overview of DRAMs 350
7.1 DRAM Basics: Internals, Operation 351
7.2 Evolution of the DRAM Architecture 357
7.3 Modern-Day DRAM Standards 367
7.4 Fully Buffered DIMM: A Compromise of Sorts 383
7.5 Issues in DRAM Systems, Briefly 386
Chapter 8. DRAM Device Organization: Basic Circuits and Architecture 388
8.1 DRAM Device Organization 388
8.2 DRAM Storage Cells 390
8.3 RAM Array Structures 393
8.4 Differential Sense Amplifier 395
8.5 Decoders and Redundancy 401
8.6 DRAM Device Control Logic 403
8.7 DRAM Device Confi guration 405
8.8 Data I/O 407
8.9 DRAM Device Packaging 408
8.10 DRAM Process Technology and Process Scaling Considerations 409
Chapter 9. DRAM System Signaling and Timing 412
9.1 Signaling System 412
9.2 Transmission Lines on PCBs 414
9.3 Termination 428
9.4 Signaling 430
9.5 Timing Synchronization 434
9.6 Selected DRAM Signaling and Timing Issues 437
9.7 Summary 443
Chapter 10. DRAM Memory System Organization 444
10.1 Conventional Memory System 444
10.2 Basic Nomenclature 444
10.3 Memory Modules 452
10.4 Memory System Topology 457
10.5 Summary 458
Chapter 11. Basic DRAM Memory-Access Protocol 460
11.1 Basic DRAM Commands 460
11.2 DRAM Command Interactions 471
11.3 Additional Constraints 485
11.4 Command Timing Summary 489
11.5 Summary 489
Chapter 12. Evolutionary Developments of DRAM Device Architecture 492
12.1 DRAM Device Families 492
12.2 Historical-Commodity DRAM Devices 493
12.3 Modern-Commodity DRAM Devices 499
12.4 High Bandwidth Path 515
12.5 Low Latency 529
12.6 Interesting Alternatives 530
Chapter 13. DRAM Memory Controller 532
13.1 DRAM Controller Architecture 532
13.2 Row-Buffer-Management Policy 534
13.3 Address Mapping (Translation) 537
13.4 Performance Optimization 546
13.5 Summary 553
Chapter 14. The Fully Buffered DIMM Memory System 554
14.1 Introduction 554
14.2 Architecture 556
14.3 Signaling and Timing 559
14.4 Access Protocol 561
14.5 The Advanced Memory Buffer 565
14.6 Reliability, Availability, and Serviceability 567
14.7 FB-DIMM Performance Characteristics 570
14.8 Perspective 575
Chapter 15. Memory System Design Analysis 576
15.1 Overview 576
15.2 Workload Characteristics 578
15.3 The RAD Analytical Framework 586
15.4 Simulation-Based Analysis 605
15.5 A Latency-Oriented Study 625
15.6 Concluding Remarks 631
Part III. Disk 634
Chapter 16. Overview of Disks 636
16.1 History of Disk Drives 636
16.2 Principles of Hard Disk Drives 641
16.3 Classifications of Disk Drives 644
16.4 Disk Performance Overview 645
16.5 Future Directions in Disks 647
Chapter 17. The Physical Layer 650
17.1 Magnetic Recording 650
17.2 Mechanical and Magnetic Components 655
17.3 Electronics 675
Chapter 18. The Data Layer 684
18.1 Disk Blocks and Sectors 684
18.2 Tracks and Cylinders 687
18.3 Address Mapping 689
18.4 Zoned-Bit Recording 693
18.5 Servo 697
18.6 Sector ID and No-ID Formatting 705
18.7 Capacity 707
18.8 Data Rate 708
18.9 Defect Management 708
Chapter 19. Performance Issues and Design Trade-Offs 712
19.1 Anatomy of an I/O 712
19.2 Some Basic Principles 716
19.3 BPI vs. TPI 723
19.4 Effect of Drive Capacity 724
19.5 Concentric Tracks vs. Spiral Track 727
19.6 Average Seek 729
Chapter 20. Drive Interface 734
20.1 Overview of Interfaces 734
20.2 ATA 737
20.3 Serial ATA 738
20.4 SCSI 740
20.5 Serial SCSI 741
20.6 Fibre Channel 742
20.7 Cost, Performance, and Reliability 744
Chapter 21. Operational Performance Improvement 746
21.1 Latency Reduction Techniques 746
21.2 Command Queueing andScheduling 750
21.3 Reorganizing Data on the Disk 758
21.4 Handling Writes 762
21.5 Data Compression 764
Chapter 22. The Cache Layer 766
22.1 Disk Cache 766
22.2 Cache Organizations 770
22.3 Caching Algorithms 776
Chapter 23. Performance Testing 782
23.1 Test and Measurement 782
23.2 Basic Tests 785
23.3 Benchmark Tests 790
23.4 Drive Parameters Tests 792
Chapter 24. Storage Subsystems 798
24.1 Data Striping 798
24.2 Data Mirroring 800
24.3 RAID 805
24.4 SAN 815
24.5 NAS 817
24.6 iSCSI 818
Chapter 25. Advanced Topics 820
25.1 Perpendicular Recording 820
25.2 Patterned Media 823
25.3 Thermally Assisted Recording 825
25.4 Dual Stage Actuator 827
25.5 Adaptive Formatting 829
25.6 Hybrid Disk Drive 831
25.7 Object-Based Storage 833
Chapter 26. Case Study 838
26.1 The Mechanical Components 838
26.2 Electronics 841
26.3 Data Layout 841
26.4 Interface 844
26.5 Cache 845
26.6 Performance Testing 845
Part IV. Cross-Cutting Issues 848
Chapter 27. The Case for Holistic Design 850
27.1 Anecdotes, Revisited 851
27.2 Perspective 862
Chapter 28. Analysis of Cost and Performance 864
28.1 Combining Cost and Performance 864
28.2 Pareto Optimality 865
28.3 Taking Sampled Averages Correctly 868
28.4 Metrics for Computer Performance 873
28.5 Analytical Modeling and the Miss-Rate Function 878
Chapter 29. Power and Leakage 882
29.1 Sources of Leakage in CMOS Devices 882
29.2 A Closer Look at Subthreshold Leakage 886
29.3 CACTI and Energy/Power Breakdown of Pipelined Nanometer Caches 890
Chapter 30. Memory Errors and Error Correction 900
30.1 Types and Causes of Failures 900
30.2 Soft Error Rates and Trends 903
30.3 Error Detection and Correction 904
30.4 Reliability of Non-DRAM Systems 915
30.5 Space Shuttle Memory System 916
Chapter 31. Virtual Memory 918
31.1 A Virtual Memory Primer 919
31.2 Implementing Virtual Memory 941
References 956
Index 990