Pathological Elements in Analog Circuit Design (eBook)

Foreword 6
Preface 8
Acknowledgements 14
Contents 15
Contributors 17
Pathological Elements in the Analysis and the Synthesis of Analog Circuits 19
1 Symbolic Analysis and Synthesis of Analog Circuits Using Nullors and Pathological Mirror Elements 20
Abstract 20
1 Introduction 21
2 Symbolic Nodal Analysis of Circuits Modeled by Nullors and Mirrors 25
3 Adjoint Transformations of Circuits Containing Nullors and Mirrors 31
4 Synthesis of Nullators, Norators, Voltage Mirrors and Current Mirrors 33
5 CMOS Implementation of Unity-Gain-Cells and Mixed-Mode Analog Circuits 37
6 Conclusions 45
Acknowledgements 46
References 46
2 Generalized Parameter Extraction Method for Symbolic Analysis of Analog Circuits Containing Pathological Elements 48
Abstract 48
1 Introduction 49
2 The Basics of GPEM 50
2.1 Feussner’s Formulae for Determinant Expansion of the Passive Circuit 50
2.2 Extraction of Controlled Sources Parameters 54
2.3 Degeneracy and Simplification of Circuits Containing Pathological Elements 56
3 Symbolic Circuit Analysis by GPEM 58
3.1 Symbolic Analysis of SISO Circuits 58
3.2 Symbolic Circuit Analysis of MISO Circuits 60
4 The Technique of Determinant Expansion of Pathological Element-Based Residual Circuits 63
4.1 Expansion of Determinants of Pathological Element-Based Residual Circuits 63
4.2 The Algorithm of Determinant Expansion Directly from HOSC of Residual Circuits 67
5 Circuit Decomposition in GPEM 71
5.1 The Downward Analysis 71
5.2 The Upward Hierarchical Analysis 76
6 Conclusion 83
Acknowledgements 84
References 84
3 Two-Graph Based Semi-topological Analysis of Electronic Circuits with Nullors and Pathological Mirrors 88
Abstract 88
1 Introduction 88
2 Primitive Signal-Flow Graphs as a Base of Semi-topological Analysis of Electronic Circuits with Nullors and Mirrors 89
3 Two-Graph Models of Nullors and Mirrors 98
3.1 Two-Graph Stamps of Nullators and Mirrors 99
3.2 Examples 101
3.2.1 The ICCII+-Base Inverting Low-Pass Filter 101
3.2.2 The Filter with Second Generation Current Conveyor 104
4 Conclusions 106
References 106
4 Circuit Analyses with Nullors 108
Abstract 108
1 Introduction 108
2 Nullor Equivalences 111
3 Loop Current Method for Circuits with Nullors 113
4 Nodal Analysis Method for Circuits with Nullors 115
5 The Generalized Topological Formula for Transfer Function Generation by Two-Graph Tree Enumeration 117
5.1 Introduction 117
5.2 Controlled Source Modelling in the Two Graphs 119
5.3 Generalized Topological Formula for Network Function Generation 124
5.4 Algorithm for Tree Enumeration in a Graph Represented on Levels 131
5.5 Algorithm for Sequential Generation of the Sign Factor 134
5.6 Automatic Generation of the Transfer Functions 138
5.7 Description of the Software Application SATE—Symbolic Analisys by Trees Enumeration 142
6 Examples 144
7 Conclusions 161
References 163
5 Symbolic Sensitivity Analysis Enhanced by Nullor Model and Modified Coates Flow Graph 165
Abstract 165
1 Introduction 166
2 Nullor-Modified Coates Flow Graph Symbolic Sensitivity Analysis Method 167
2.1 Composing of an Equivalent Nullor Model 168
2.1.1 A Nullator or More Nullators Are Connected with the Source Node 169
2.1.2 A Norator Is Connected Between Two Nullators in the Equivalent Nullor Model 170
2.1.3 A Norator or More Norators Are Connected with the Source Node 171
2.1.4 A Norator and a Nullator Are Connected with the Source Node 173
2.1.5 Norators Have a Common Node in the Equivalent Nullor Model 174
2.2 Determination of the Partial Transfer Functions and the First-, Second-Order and Multiparameter Symbolic Sensitivity by Nullor Model 176
2.3 Examples 178
3 SANMCFG Method Versus TI 186
3.1 Comparison of Arithmetical Operations 186
3.2 Comparison of Circuit Insights 189
4 Conclusion 190
References 191
6 Synthesis of Electronic Circuits Structures on the Basis of Active Switches 193
Abstract 193
1 Introduction 193
2 Primitive Signal-Flow Graphs as a Base of a Combinatorial Approach for Constructing Analog Building Blocks 195
3 Searching for New Circuits Structures by a Combinatorial Approach 196
3.1 Circuits Structures with One Resistor 196
3.2 Circuits Structures with Two Resistors 199
3.3 Circuits Structures with Three and Four Resistors 207
3.4 Circuits with Resistors and Passive Elements 210
4 Practical Implementations 211
5 Conclusion 215
References 215
Pathological Elements in the Design of Analog Circuits 217
7 Applications of the Voltage Mirror-Current Mirror in Realizing Active Building Blocks 218
Abstract 218
1 Introduction 218
2 The Voltage Mirror and Current Mirror 220
3 Realization of VM and CM Using Nullor Elements and Resistors 221
4 The VM and CM Realizing Nullators and Norators 222
5 The VM-CM Pair Realizing Active Building Blocks 225
5.1 Realization of the Op Amp Family 226
5.2 Realization of the Current Conveyor Family 227
5.3 Realization of Current Follower and Current Inverter 229
6 Realization of Controlled Sources 230
6.1 Realization of VCVS Using VM-CM Pair 230
6.2 Realization of CCCS Using VM-CM Pair 233
6.3 Realization of TA Using VM-CM Pair 233
7 The OMA and the VM-Norator Pair 235
8 Conclusions 237
References 237
8 Circuit Biasing Using Fixator-Norator Pairs—A Tutorial 239
Abstract 239
1 Introduction 239
2 Nullification 243
2.1 Port Nullification 243
2.2 Multi-port Networks 244
3 Local Biasing 249
3.1 Local Biasing of Devices 249
3.2 Properties of Local Biasing 250
4 Local Biasing Devices With Reduced Number of Supplies 252
4.1 DC Nullator Representation of Devices 255
5 Fixator-Norator Pairs in Biasing Designs 257
5.1 Fixator 257
5.2 Rules Governing Fixators and Norators 258
5.3 Fixators and Local Biasing 259
5.4 Fixators Norator Pairs (FNP) 260
6 Fixator-Norator Pairs in VLSI Biasing Designs 266
7 Conclusion 271
References 272
9 Fixator-Norator Pair Based Design of Analog Circuits 274
Abstract 274
1 Introduction 274
2 The Tool 276
3 Source Allocation and Source Transformation 277
4 Biasing Design of Analog Circuits 282
5 Design of Analog Integrated Circuits 285
6 Design of Feedback Networks 292
7 Complete Design of Analog Circuits 295
8 Summary 299
References 299
10 Application of Fixator-Norator Pairs in Analog Circuit Design 301
Abstract 301
1 Introduction 302
2 Fixator-Norator Pairs 303
2.1 Fixator and Norator 303
2.2 Fixator-Norator Pairs in Linear Circuits 304
2.3 Rules Governing Fixators and Norators 307
3 Use of FNP in Biasing Design 308
4 Designing for Gain, and Input and Output Impedances 311
5 Designing Active Load and Current Mirrors Using FNP 318
5.1 Active Load Design 320
6 Designing Analog VLSI Circuits 321
7 Nullors in Amplifier Design for Bandwidth 327
7.1 Design Procedure for Bandwidth Matching 327
7.2 Implementation Procedures 330
7.3 Design Examples 331
7.4 Designing for Bandwidth with Multiple Feedbacks 334
8 Conclusion 339
References 340
Nullor-Based Negative-Feedback Memristive Amplifiers: Symbolic-Oriented Modelling and Design 341
1 Introduction 342
1.1 The Nullor 342
1.2 The Memristor 343
2 Development of the Memristor Model 345
3 Memristive Amplifiers 349
3.1 Memristive Voltage Amplifier 350
3.2 Transmemristance Amplifier 352
3.3 Transmemductance Amplifier 352
3.4 Memristive Current Amplifier 354
4 Noise Analysis 355
4.1 Noise in the Memristive Amplifiers 356
5 Harmonic Analysis 359
5.1 Harmonic Analysis for the Memristive Voltage Amplifier 359
5.2 Harmonic Analysis for the Transmemristance Amplifier 361
5.3 Harmonic Analysis for the Transmemductance Amplifier 363
5.4 Harmonic Analysis for the Current Amplifier 364
6 Implementing the Nullor with a Memistor 365
6.1 A Case Study: The Transmemristance Amplifier 367
7 Conclusions 369
8 Appendix 369
References 370