Advanced Flip Chip Packaging (eBook)

Preface 6
Contents 8
Chapter 1: Market Trends: Past, Present, and Future 9
1.1 Flip Chip Technology Overview and Early Beginnings 9
1.2 Wafer Bumping Technology Overview 10
1.3 Evaporation (C4) 11
1.3.1 Stencil Printing 11
1.3.2 Electroplating 13
1.3.3 Solder Dam 13
1.3.4 Plating Outside a Defined Structure 15
1.4 Wafer Bump Summary 17
1.4.1 Substrate Technology 17
1.5 Flip Chip Industry and Infrastructure Development 18
1.6 Flip Chip Market Trends Covering C4 22
1.7 Flip Chip Market Drivers Including the Need for More Package Co-design and IC-Package-System Co-design Involving Cu/Low K ... 24
1.8 Migration of Flip Chip from IDM´s to SAT´s Providers 26
1.9 Implications of the Advent of Tighter Environmental Regulations Covering Underfill, Solder, Structural Design, etc. 28
1.10 Mounting Cost Pressures and Implications for Flip Chip, etc. 28
References 29
Chapter 2: Technology Trends: Past, Present, and Future 30
2.1 Evolution of Flip Chip Technologies in Response to IC and System Technology Trends 30
2.2 Evolution of First Level Packaging 34
2.2.1 Thermal Demands 34
2.2.2 Increased Chip Size 34
2.2.3 Restriction of Hazardous Substances 36
2.2.4 Compliance Cost, and Future RoHS Directive 37
2.2.5 Choice of Sn 38
2.2.6 Solder Void 40
2.2.7 Soft Error and Alpha Emission 40
2.3 First Level Packaging Challenges 41
2.3.1 Weaker BEOL Structures 41
2.3.2 C4 Electromigration 42
2.3.3 Cu Pillar Technology 44
2.4 IC Technology Roadmaps: More Moore and More Than Moore 45
2.4.1 Improvements in Laminate Ground Rules 48
2.5 3D Flip Chip SiPs for Handhelds Require IC-Package-System Co-design 48
2.5.1 SIP Engineering Challenges and Co-design Tool 49
2.6 PoP and Stacked Packages 51
2.6.1 Embedded Chip Packages 52
2.6.2 Folded Stacked Packages 53
2.7 Emerging Flip Chip Technologies 54
2.8 Summary 57
References 57
Chapter 3: Bumping Technologies 60
3.1 Introduction 60
3.2 Materials and Processes for Bumping Technology 61
3.2.1 Metals for Wafer Bumping 61
3.2.1.1 Under Bump Metallization 62
3.2.1.2 Bumping Technologies 63
3.2.1.3 Bump Metallurgy 73
Bumps Based on Gold and AuSn 73
Bumps Based on Solder 75
Copper Posts (Pillars) 76
Plating of Ni 78
3.2.1.4 Plating of Alloys 78
3.3 Recent Advances on Bumping Technologies 83
3.3.1 Low Cost Solder Bumping Process: Solder Bump Maker 83
3.3.2 Nanoporous Interconnect 83
3.3.3 Inclined Microbump 83
3.3.4 Fine Pitch Imprinting Bumping 85
3.3.5 Solder Bumping by Liquid Droplet Microgripper 86
3.3.6 CNT Bumps 88
References 90
Chapter 4: Flip-Chip Interconnections: Past, Present, and Future 92
4.1 Evolution of Flip-Chip Interconnection Technologies 93
4.1.1 High-Pb-Based Solder Joint 94
4.1.2 High-Pb Solder on Chip Joined to Eutectic Solder on Laminate Carrier 94
4.1.3 Pb-Free Solder Joint 96
4.1.4 Cu Pillar Joint 96
4.2 Evolution of Enabling Assembly Technologies 98
4.2.1 Wafer Thinning and Wafer Dicing (Covering Cu/low k Devices) 98
4.2.2 Wafer Bumping 99
4.2.3 Flux and Flux Cleaning 102
4.2.4 Reflow Soldering, Thermo-compression Bonding 103
4.2.5 Underfill and Over-Mold 105
4.2.6 Quality Assurance Methodologies 107
4.3 C4NP Technology 108
4.3.1 C4NP Wafer Bumping Processes 109
4.3.2 Mold Fabrication and Solder Transfer to Wafer 109
4.3.3 Wafer Bumping Yield Improvements 110
4.3.4 C4NP Advantages: Alloy Flexibility 113
4.4 Fabrication of Cu Pillar Bumps 115
4.5 Substrate Bumping Technologies 115
4.6 Pb-Free Solders for Flip-Chip Applications 122
4.6.1 Properties of Pb-Free Solders 123
4.6.2 Solidification, Microstructure, and Undercooling 125
4.7 Interfacial Reactions in Pb-Free, Flip-Chip Joints 126
4.7.1 Ball-Limiting Metallurgy or Under Bump Metallization 126
4.7.2 Substrate Metallization 128
4.7.3 Interfacial Reactions in Pb-Free Solder Joints 129
4.8 Reliability of Flip-Chip Interconnect Structure 133
4.8.1 Thermal Fatigue 133
4.8.2 Drop Impact Reliability 134
4.8.3 Chip-Package-Interaction: Interlayer Dielectric Cracking During Module Assembly 136
4.8.4 Electromigration Reliability 140
4.8.5 Sn Pest 148
4.9 Future Trends in Flip-Chip Technology 148
4.9.1 Conventional Micro-Solder Joint 149
4.9.2 Metal-to-Metal Solid-State Diffusion Bonding 151
4.10 Concluding Remark 153
References 154
Chapter 5: Flip Chip Underfill: Materials, Process, and Reliability 162
5.1 Introduction 162
5.2 Conventional Underfill Materials and Process 165
5.3 Characterizations of Underfill Materials 167
5.3.1 Differential Scanning Calorimeter Measured Curing Kinetics 167
5.3.2 DSC Measured Tg 170
5.3.3 TMA Measured Coefficient of Thermal Expansion 171
5.3.4 DMA Measured Dynamic Moduli 172
5.3.5 TGA Measured Thermal Stability 173
5.3.6 Flexure Test 174
5.3.7 Viscosity Measurement 175
5.3.8 Adhesion of the Underfill to Die Passivation 175
5.3.9 Moisture Absorption 176
5.4 Reliability of Flip Chip Underfill Packages 176
5.4.1 Effect of Passivation Layer 179
5.4.2 Adhesion Degradation Versus 85/85 Aging Time 180
5.4.3 Improvement of Adhesion Hydrolytic Stability Through Coupling Agents 183
5.5 New Challenges to Underfill 185
5.6 No-Flow Underfill 188
5.6.1 Approaches of Incorporating Silica Fillers into No-Flow Underfill 192
5.7 Molded Underfill 195
5.8 Wafer Level Underfill 197
5.9 Summary 201
References 202
Chapter 6: Conductive Adhesives for Flip-Chip Applications 207
6.1 Introduction 207
6.2 Anisotropically Conductive Adhesives/Films 208
6.2.1 Overview of ACAs/ACFs 208
6.2.2 Categories 208
6.2.3 Adhesive Matrix 209
6.2.4 Conductive Fillers 210
6.2.4.1 Solid Metal Particles 210
6.2.4.2 Non-metal Particles with Metal Coating 210
6.2.4.3 Metal Particles with Insulating Coating 210
6.2.5 Flip-Chip Applications Using ACAs/ACFs 210
6.2.5.1 ACA Flip Chip for Bumped Dies 211
Two Filler Systems 211
Coated Plastic Filler 212
Solder Filler Systems 212
Ni Filler 213
6.2.5.2 ACA Bumped Flip Chips on Glass Chip Carriers 214
Selective Tacky Adhesive Method 214
The MAPLE Method 215
6.2.5.3 ACA Bumped Flip Chips for High Frequency Applications 216
6.2.5.4 ACA for Unbumped Flip Chips 216
Gold-Coated Nickel Filler 217
Ni/Au Coated Silver Filler 217
Conductive Columns 217
6.2.6 Failure Mechanism of ACA/ACF Interconnections 218
6.2.6.1 Oxidation of Non-noble Metals 219
6.2.6.2 Loss of Compressive Force 219
6.2.7 Recent Advances in Nano-ACAs/ACFs 219
6.2.7.1 Low Temperature Sintering of Nano-Ag-Filled ACAs/ACFs 219
6.2.7.2 Self-Assembled Monolayers for Nano-ACAs/ACFs 220
6.2.7.3 Silver Migration Control in Nano-Silver Filled ACAs 222
6.2.7.4 ACF with Straight-Chain-Like Nickel Nanoparticles 224
6.2.7.5 Nanowire ACFs for Ultrafine Pitch Flip-Chip Interconnection 224
6.2.7.6 In-Situ Formation of Nano-Conductive Fillers in ACAs/ACFs 226
6.3 Isotropically Conductive Adhesives 226
6.3.1 Introduction 226
6.3.1.1 Percolation Theory of Conduction 226
6.3.1.2 Adhesive Matrix 227
6.3.1.3 Conductive Fillers 229
Pure Silver vs. Ag-Coated Fillers 230
Particle Shape and Size 230
Nano-Sized Fillers 230
Silver-Copper Fillers 231
Cu Fillers 231
Low-Melt Fillers 233
6.3.2 Flip-Chip Applications Using ICAs 234
6.3.2.1 ICA Process for Unbumped Chips 234
Flip Chip with Printed ICA Bumps 234
UBM Deposition 235
ICA Printing 235
ICA Bump Curing 236
Underfilling 236
Flip Chip with Micromachined ICA Bumps 236
6.3.2.2 Metal-Bumped Flip-Chip Joints 239
6.3.2.3 Carbon Nanotube Flip Chip 240
6.3.3 ICAs for Advanced Packaging Applications 242
6.3.3.1 Solar Cell 242
6.3.3.2 3D Stacking 244
6.3.3.3 Microspring 244
6.3.4 High Frequency Performance of ICA Joints 247
6.3.5 Reliability of ICA Joints 247
6.3.6 Recent Advances on Nano-ICAs 250
6.3.6.1 ICAs with Silver Nanowires 250
6.3.6.2 Effect of Nano-Sized Silver Particles on the Conductivity of ICAs 251
6.3.6.3 ICAs Filled with Aggregates of Nano-sized Ag Particles 252
6.3.6.4 ICAs Filled with Nano-sized Ni Particles 252
6.3.6.5 Nano-ICAs Filled with CNT 253
Electrical and Mechanical Characterization of CNT-Filled ICAs 253
Effect of Adding CNTs to the Electrical Properties of ICAs 254
Composites Filled with Surface Treated CNT 255
6.4 Nonconductive Adhesive for Flip-Chip Applications 255
6.4.1 Recent Developments on NCA Flip Chip 257
6.4.1.1 NCAs with Low CTE 257
6.4.1.2 Fine Pitch Chip-on-Flex by Pre-applied Wafer Level Adhesives 258
6.4.1.3 Fast Curing NCA 259
6.4.1.4 NCAs Versus ACAs in Flex Circuits 259
References 259
Chapter 7: Substrate Technology 268
7.1 Introduction 268
7.2 Type of Construction 269
7.2.1 Sequential Build-Up Structure 270
7.2.2 Z-Stack Structure 271
7.3 Sequential Build-Up Substrate 271
7.3.1 Process Flow 272
7.3.2 Conductor Line 273
7.3.3 Micro-Via Hole 283
7.3.4 Pad Finish 292
7.3.5 Chip Package Interaction 301
7.3.6 Reliability 310
7.3.7 Historical Milestone 317
7.4 Z-Stack Type Substrate 319
7.4.1 Z-Stack Substrate With Pattern Transfer 319
7.4.2 Any Layer Via Substrate 324
7.4.3 Embedded Component Substrate 324
7.4.4 Substrate With PTFE Material 328
7.5 Challenges 329
7.5.1 Coreless Structure 329
7.5.2 Trench Structure 332
7.5.3 Ultralow CTE 333
7.5.4 Substrate for Stacked Chip 334
7.5.5 Optical Wave Guide 337
7.6 Ceramic Substrate 338
7.7 Roadmap 338
7.7.1 JEITA 338
7.7.2 ITRS 342
7.8 Summary 343
References 343
Chapter 8: IC-Package-System Integration Design 345
8.1 Integrated Chip-Package-System: What, How, and Why? 347
8.1.1 Introduction 347
8.1.1.1 Overview 347
8.1.2 Design Explorations 349
8.1.2.1 On-Chip Design Decisions 351
I/O Circuit Design 351
I/O Buffer Physical Planning 352
On-Chip Power Design and Planning 353
8.1.2.2 Package Design and Exploration 353
Package Stack-Up Order 354
Substrate Layer Assignment 354
Voltage Domain Planning 354
8.1.3 Modeling and Analysis Decisions 356
8.1.4 ICPS Design Problems 356
8.1.4.1 Design and Planning of Power Delivery System 357
8.1.4.2 Design and Planning of Signal Interface 357
Signal Interface Characterization 357
8.2 Decoupling Capacitor Insertion 359
8.2.1 Introduction 359
8.2.2 Electrical Models 361
8.2.2.1 Package Model 361
8.2.2.2 Decoupling Capacitor Model 362
8.2.2.3 Model of I/O Cells 362
8.2.3 Impedance Metric and Its Incremental Computation 364
8.2.4 Noise Metric 366
8.2.5 Simulated-Annealing-Based Decap Insertion 367
8.2.5.1 Settings 367
8.2.5.2 Algorithm 368
8.2.5.3 Results 369
Case 1 369
Case 2 370
8.2.5.4 Runtime 371
8.2.6 Sensitivity-Based Decap Insertion 372
8.2.6.1 Improved Model and Problem Formulation 372
8.2.6.2 Parameterized Circuit Equation 374
8.2.6.3 I/O Current Correlation and Spectral Clustering 376
8.2.6.4 Localized Integrity Analysis 378
Network Decomposition 378
Triangular Block-Structured Reduction 379
8.2.6.5 Algorithm and Experimental Results 381
Sensitivity-Based Optimization 381
Experimental Results 382
8.3 TSV-Based 3D Stacking: The Good, the Bad, and the Powerful 385
8.3.1 Introduction About 3D IC Stacking Techniques 385
8.3.2 Challenges 388
8.3.2.1 Thermal and Power Distribution Issues of 3D IC 388
8.3.2.2 Testing Issues of 3D IC 390
8.3.3 Solutions 393
8.3.3.1 3D IC Design Automation Considering Dynamic Power and Thermal Integrity 393
TSV Allocation Problem 394
Algorithm 395
Complexity Compression of States 395
Complexity Compression of I/Os 396
Dynamic Integrity and Sensitivity by Structured and Parameterized Macromodel 398
Results 400
Experimental Setup 400
Results Analysis 400
8.3.3.2 Fault-Tolerant 3D Clock Scheme 402
Clock Design with TFU 402
Algorithm 404
TSV Fault-Tolerant Unit 404
TSV Pairing and Buffer Insertion 404
TFU Integration with Clock Tree Synthesis 405
Results 407
Experimental Setup 407
Results Analysis 408
8.4 Summary 410
References 411
Chapter 9: Thermal Management of Flip Chip Packages 417
9.1 Introduction 418
9.2 Heat Transfer Fundamentals 419
9.3 Electro-thermal Analog Model 422
9.4 Thermal Management Objectives 424
9.5 Thermal Management at the Die and Package Level 425
9.6 Hot Spots in Chip Dies 427
9.7 Analytical Modeling of Chip Hot Spots 428
9.8 Chip Thinning 434
9.9 Thermal Interface Materials 434
9.10 System Level Thermal Management 436
9.11 Conduction Heat Spreaders 438
9.12 Heat Pipes 438
9.13 Air-Cooled Heat Sinks 441
9.14 Liquid Cooled Cold Plates 442
9.15 Internal Hybrid Liquid-Air Cooling Systems 444
9.16 Refrigeration Cooled Systems 446
9.17 Emerging Research Areas and Technologies 451
9.18 Direct Immersion Cooling 451
9.19 3D Chip Stacks 455
9.20 Advanced Thermal Interfaces 457
9.21 Synthetic Jets and Actuated Flow Devices 458
9.22 Multi-Core Focused Chip Cooling 459
9.23 Thermoelectric Enhanced Cooling 459
9.24 Measurements and Modeling 462
9.25 Package Thermal Measurements 462
9.26 Temperature Measurement Device and Method 464
9.27 Temperature Measurement Standards 464
9.28 Compact Thermal Models 465
9.29 FEM/CFD Modeling 467
References 469
Chapter 10: Thermo-mechanical Reliability in Flip-Chip Packages 474
10.1 Overview of Thermo-mechanical Reliability Issues in Flip-Chip Packages 475
10.2 Thermal Deformation in Flip-Chip Assembly 477
10.2.1 Consistent Composite Plate Model 477
10.2.2 Free Thermal Deformation 479
10.2.3 Die Stress Estimation with Bi-material Plate Model 481
10.2.4 Minimizing Chip-Packaging Interaction 483
10.2.5 Summary of Thermal Deformation in Flip-Chip Assembly 487
10.3 Solder Bump Reliability in Flip-Chip Assembly 487
10.3.1 Thermal Strain Measurement in Solder Bumps 488
10.3.2 Constitutive Equation for Solder 491
10.3.3 Reliability Modeling for Solder Joint 496
10.3.4 Underfill Adhesion Strength on Solder Bump Reliability 500
10.3.5 Summary of Solder Bump Reliability 502
References 503
Chapter 11: Interfacial Reactions and Electromigration in Flip-Chip Solder Joints 505
11.1 Introduction 506
11.2 Interfacial Reactions of Lead-Free Solders with Substrates 507
11.2.1 Dissolution and Its Kinetics During Reflow 508
11.2.2 Reaction of Lead-Free Solders with Cu-Based Pads 512
11.2.3 Reaction of Lead-Free Solders with Ni-Based Pads 512
11.2.3.1 Uncomplicated Cu Concentration Effect 513
11.2.4 Cross-interaction Between Cu and Ni Across a Solder Joint 518
11.2.4.1 Cross-interaction During Reaction with Molten Solders (Reflow) 519
11.2.4.2 Cross-interaction During Reaction with Solid Solders (Aging) 521
11.2.5 Effect of Alloying with Other Active Elements 521
11.2.5.1 Fe, Co, and Ni Additions 522
11.2.5.2 Zn Addition 523
11.2.5.3 Cu Addition 525
11.2.6 Effect of Small Solder Volume 525
11.2.6.1 Exhaustion of the Active Element Due to Smaller Solder Volume 526
11.2.6.2 Excessive Intermetallic Formation Due to Small Solder Volume 529
11.3 Electromigration in Flip-Chip Solder Joints 530
11.3.1 Fundamentals of Electromigration 531
11.3.2 Effect of Current Stressing on Solder and the Resulting Failure Mechanism 534
11.3.2.1 Low Critical Product of Solder Alloys 535
11.3.2.2 Current Crowding in Flip-Chip Solder Joints 536
11.3.2.3 Pancake-Type Void Formation Within Solder on the Cathode Side 536
11.3.2.4 Comparison Between Eutectic Sn-Pb and Sn-Ag-Cu Solders Under Current Stressing 541
11.3.3 Effect of Current Stressing on UBM and the Resulting Failure Mechanism 541
11.3.3.1 Dissolution of Cu UBM 542
11.3.3.2 Dissolution of Ni UBM 544
11.3.3.3 Temperature Effect on the UBM Dissolution 548
11.3.4 Mean-Time-to Failure of Flip-Chip Solder Joints 551
11.3.5 Mitigation Strategy Against Electromigration 552
11.4 Emerging Issues 554
References 555