Front Cover 1
ARM System Developer’s Guide Designing and Optimizing System Software 4
Copyright Page 5
Contents 6
About the Authors 3
Preface 12
Chapter 1. ARM Embedded Systems 17
1.1 The RISC design philosophy 18
1.2 The ARM Design Philosophy 19
1.3 Embedded System Hardware 20
1.4 Embedded System Software 26
1.5 Summary 29
Chapter 2. ARM Processor Fundamentals 33
2.1 Registers 35
2.2 Current Program Status Register 36
2.3 Pipeline 43
2.4 Exceptions, Interrupts, and the Vector Table 47
2.5 Core Extensions 48
2.6 Architecture Revisions 51
2.7 ARM Processor Families 52
2.8 Summary 57
Chapter 3. Introduction to the ARM Instruction Set 61
3.1 Data Processing Instructions 64
3.2 Branch Instructions 72
3.3 Load-Store Instructions 74
3.4 Software Interrupt Instruction 87
3.5 Program Status Register Instructions 89
3.6 Loading Constants 92
3.7 ARMv5E Extensions 93
3.8 Conditional Execution 96
3.9 Summary 98
Chapter 4. Introduction to the Thumb Instruction Set 101
4.1 Thumb Register Usage 103
4.2 ARM-Thumb Interworking 104
4.3 Other Branch Instructions 106
4.4 Data Processing Instructions 107
4.5 Single-Register Load-Store Instructions 110
4.6 Multiple-Register Load-Store Instructions 111
4.7 Stack Instructions 112
4.8 Software Interrupt Instruction 113
4.9 Summary 114
Chapter 5. Efficient C Programming 117
5.1 Overview of C Compilers and Optimization 118
5.2 Basic C Data Types 119
5.3 C Looping Structures 127
5.4 Register Allocation 134
5.5 Function Calls 136
5.6 Pointer Aliasing 141
5.7 Structure Arrangement 144
5.8 Bit-fields 147
5.9 Unaligned Data and Endianness 150
5.10 Division 154
5.11 Floating Point 163
5.12 Inline Functions and Inline Assembly 163
5.13 Portability Issues 167
5.14 Summary 169
Chapter 6. Writing and Optimizing ARM Assembly Code 171
6.1 Writing Assembly Code 172
6.2 Profiling and Cycle Counting 177
6.3 Instruction Scheduling 177
6.4 Register Allocation 185
6.5 Conditional Execution 194
6.6 Looping Constructs 197
6.7 Bit Manipulation 205
6.8 Efficient Switches 211
6.9 Handling Unaligned Data 215
6.10 Summary 218
Chapter 7. Optimized Primitives 221
7.1 Double-Precision Integer Multiplication 222
7.2 Integer Normalization and Count Leading Zeros 226
7.3 Division 230
7.4 Square Roots 252
7.5 Transcendental Functions: log, exp, sin, cos 255
7.6 Endian Reversal and Bit Operations 262
7.7 Saturated and Rounded Arithmetic 267
7.8 Random Number Generation 269
7.9 Summary 270
Chapter 8. Digital Signal Processing 273
8.1 Representing a Digital Signal 274
8.2 Introduction to DSP on the ARM 283
8.3 FIR filters 294
8.4 IIR Filters 308
8.5 The Discrete Fourier Transform 317
8.6 Summary 328
Chapter 9. Exception and Interrupt Handling 331
9.1 Exception Handling 332
9.2 Interrupts 338
9.3 Interrupt Handling Schemes 347
9.4 Summary 378
Chapter 10. Firmware 381
10.1 Firmware and Bootloader 381
10.2 Example: Sandstone 386
10.3 Summary 393
Chapter 11. Embedded Operating Systems 395
11.1 Fundamental Components 395
11.2 Example: Simple Little Operating System 397
11.3 Summary 414
Chapter 12. Caches 417
12.1 The Memory Hierarchy and Cache Memory 418
12.2 Cache Architecture 422
12.3 Cache Policy 432
12.4 Coprocessor 15 and Caches 437
12.5 Flushing and Cleaning Cache Memory 437
12.6 Cache Lockdown 457
12.7 Caches and Software Performance 470
12.8 Summary 471
Chapter 13. Memory Protection Units 475
13.1 Protected Regions 477
13.2 Initializing the MPU, Caches, and Write Buffer 479
13.3 Demonstration of an MPU system 492
13.4 Summary 501
Chapter 14. Memory Management Units 505
14.1 Moving from an MPU to an MMU 506
14.2 How Virtual Memory Works 507
14.3 Details of the ARM MMU 515
14.4 Page Tables 515
14.5 The Translation Lookaside Buffer 520
14.6 Domains and Memory Access Permission 524
14.7 The Caches and Write Buffer 526
14.8 Coprocessor 15 and MMU Configuration 527
14.9 The Fast Context Switch Extension 529
14.10 Demonstration: A Small Virtual Memory System 534
14.11 The Demonstration as mmuSLOS 559
14.12 Summary 559
Chapter 15. The Future of the Architecture 563
15.1 Advanced DSP and SIMD Support in ARMv6 564
15.2 System and Multiprocessor Support Additions to ARMv6 574
15.3 ARMv6 Implementations 577
15.4 Future Technologies beyond ARMv6 577
15.5 Summary 580
Appendix A. ARM and Thumb Assembler Instructions 583
A.1 Using This Appendix 583
A.2 Syntax 584
A.3 Alphabetical List of ARM and Thumb Instructions 587
A.4 ARM Assembler Quick Reference 634
A.5 GNU Assembler Quick Reference 645
Appendix B. ARM and Thumb Instruction Encodings 651
B.1 ARM Instruction Set Encodings 651
B.2 Thumb Instruction Set Encodings 652
B.3 Program Status Registers 659
Appendix C. Processors and Architecture 661
C.1 ARM Naming Convention 661
C.2 Core and Architectures 661
Appendix D. Instruction Cycle Timings 665
D.1 Using the Instruction Cycle Timing Tables 665
D.2 ARM7TDMI Instruction Cycle Timings 667
D.3 ARM9TDMI Instruction Cycle Timings 668
D.4 StrongARM1 Instruction Cycle Timings 669
D.5 ARM9E Instruction Cycle Timings 670
D.6 ARM10E Instruction Cycle Timings 672
D.7 Intel XScale Instruction Cycle Timings 673
D.8 ARM11 Cycle Timings 675
Appendix E. Suggested Reading 681
E.1 ARM References 681
E.2 Algorithm References 681
E.3 Memory Management and Cache Architecture (Hardware Overview and Reference) 682
E.4 Operating System References 682
Index 683