Dynamically Reconfigurable Systems (eBook)

Foreword 5
Preface 7
Contents 10
Contributors 20
Part I Architectures 25
Development and Synthesis of Adaptive Multi-grained Reconfigurable Hardware Architecture for Dynamic Function Patterns 26
Introduction 26
HoneyComb Architecture 28
Architectural Considerations 28
HoneyComb Overview 31
Communication Network and Online Adaptive Routing Technique 32
Datapath Cells (DPHC) 34
Memory Cells (MEMHC) 36
Input/Output Cells (IOHC) 36
Power Saving Techniques 38
Tool Support 38
HoneyComb Assembler and the Hierarchical Programming Model 39
HoneyComb Language (HCL) and Compiler 40
Debugging Tool-HoneyComb Viewer 41
Super-Configuration Generator, Configuration Editor and Configuration Manager 41
Hierarchy Generator 42
Application and Synthesis Results 42
Future Work 45
Conclusion 46
References 46
Reconfigurable Components for Application-Specific Processor Architectures 48
Introduction 48
Parameterized eFPGA Target Architecture 50
Physical Implementation of Application Class Specific eFPGAs 55
Mapping and Configuration 58
Examples of (Stand Alone) eFPGAs as SoC Building Blocks 60
Examples of eFPGAs as Coprocessors to Standard RISC Processor Kernels 62
General-Purpose Processors Coupled with eFPGAs 64
ASIPs Coupled with eFPGA-Based Accelerators 64
ASIP 64
ASIP-eFPGA Coupling Mechanisms 65
Performance and Cost Evaluation 67
Examples of eFPGAs as Coprocessors to Application Specific Instruction Processors (rASIPs) 68
Conclusion 69
References 70
Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform 73
Introduction 74
Drawbacks of Existing Dynamically Reconfigurable Systems 74
The Erlangen Slot Machine 77
Architecture Overview 77
The BabyBoard 78
Computation and Reconfigurable Engine 78
The Reconfiguration Manager 79
Memory 79
Debug Lines 80
The MotherBoard 80
Inter-module Communication 81
Communication Between Adjacent Modules 82
Communication via Shared Memory 82
Communication via RMB 82
Communication via the Crossbar 83
Reconfiguration Manager 84
Flexible Plugin Architecture 84
Reconfiguration Scenarios 86
Implementation Results 86
Case Study: Video and Audio Streaming 87
Usage of the ESM in Different Fields 89
Conclusions 91
References 92
Part II Design Methods and Tools-Modeling, Evaluation and Compilation 94
Models and Algorithms for Hyperreconfigurable Hardware 95
Introduction 95
Hyperreconfigurable Machines 96
2-level Reconfiguration 96
Multi-level Reconfiguration 100
Heterogeneous Multi-level Reconfiguration 100
Example Architectures and Test Cases 101
Fine-granular Hyperreconfigurable Machine 101
Coarse-granular Hyperreconfigurable Machine 102
The Partition into Hypercontexts Problem 103
Experiments and Results 104
Diverse Granularity in Multi-level Reconfigurable Systems 106
Partial Reconfiguration and Hyperreconfiguration 110
Frame Model of Partially Reconfigurable Architectures 110
Results 112
Conclusions 113
References 113
Evaluation and Design Methods for Processor-Like Reconfigurable Architectures 115
Introduction 115
Benefits and Costs of Processor-Like Reconfiguration 117
CRC Model 117
Compiler 119
Evaluation 120
Specialization/Instruction Set Extension 122
Methodology 124
Study Case: Multipoint FFT for Scalable OFDMA Based Systems 125
Optimizing Power 128
Optimizing Power by Instruction Set Extensions 128
Optimizing Power by Dual-VDD Architectures 128
The Dual-VDD Architecture Model 129
Delay and Area 130
Power Estimation 130
Optimizing External Reconfiguration 131
Multi-Context Configuration Prefetching 132
Speculative Configuration Prefetching 133
Experimental Results 134
Conclusion 135
References 135
Adaptive Computing Systems and Their Design Tools 137
Introduction 137
Execution Model 138
ACS Architecture 140
Reconfigurable System-on-Chip Architecture 140
Operating System Integration 141
RCU-SPP Signalling 142
Shared Virtual Memory 143
Evaluation 145
Hardware/Software Co-compilation Flow 145
Overview 145
Profile-Based Inlining and Partitioning 146
CMDFG Intermediate Representation 147
CoCoMa Controller Model 149
Infrastructure 151
Parametrized Module Library 151
Physical Design Aspects 151
Reconfiguration Scheduling 153
Lessons Learned 154
Future Work 156
Conclusions 156
References 157
PolyDyn-Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs 159
Introduction 159
Related Work 161
Methodology 162
General Concept 163
Lifetime and Conflict Management 165
Derived Interface Classes 167
Modelling Example: Car Audio System 168
Coding Style: From C++ Polymorphism to OSSS+R 169
Devices and Timing 171
Simulation 172
Synthesising OSSS+R 173
From OSSS+R to RT Level 173
Recon-Object 175
Reconfiguration Controller 175
Method Calls 175
RTL Simulation Model 175
From RTL to Bitstreams 176
Evaluation 176
Conclusion and Future Work 177
References 177
Part III Design Methods and Tools-Optimization and Runtime Systems 179
Design Methods and Tools for Improved Partial Dynamic Reconfiguration 180
Introduction 180
Motivation 182
Reconfigurable Module Architecture and Partitioning 183
Reconfiguration State Graph 184
Module Mapping and Virtual Architecture 185
High-Level Synthesis of Reconfigurable Modules 187
Resource Type Binding 188
Resource Instance Binding 189
Control Generation 191
Experiments 192
Experimental Setup 192
Resource Type Binding Methods 192
Resource Instance Binding Methods 192
Implementation Scenarios 192
Benchmark Characteristics 193
Benchmark Results and Discussion 193
System Design for Efficient Partial Dynamic Reconfiguration 197
References 199
Dynamic Partial Reconfiguration by Means of Algorithmic Skeletons-A Case Study 201
Introduction 201
Overview of the Overall System 203
Library of Algorithmic Skeletons 206
Algorithmic Skeletons for Defining the Structure of the Design 206
Algoskels 207
Algorithmic Skeletons for Partial Reconfigurable Systems 208
Application Scenario: Channel Vocoder Analyzer 209
Conclusion 215
References 215
ReCoNodes-Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices 217
Introduction 217
Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device 219
Two-dimensional Strip Packing 221
Defragmentation Approach and Computational Results 222
Online Packing 222
Minimizing Communication Cost for Reconfigurable Slot Modules 224
Mathematical Model 225
Minimizing the Number of Parallel Segments 226
Minimize Segment-Constrained Bandwidth 227
Case Study and Results 228
No-break Dynamic Defragmentation of Reconfigurable Devices 229
Model and Problem Description 230
Problem Complexity and Moderate Densities 231
A Heuristic Method 231
Scheduling Dynamic Resource Requests 232
An ILP 233
Heuristic Methods 235
References 237
ReCoNets-Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections 240
Introduction 240
System Model 242
A Distributed Operating System Architecture for Networked Embedded Systems 243
Self-healing and Self-adaptiveness 244
Discrete Diffusion-Based Task Binding 246
Replica Placement 248
Hardware/Software Task Migration 251
Hardware/Software Morphing 252
Hardware/Software Checkpointing 254
Design and Synthesis of ReCoNets 255
Design Space Exploration 255
Dependability Analysis 256
Demonstrator 257
References 259
Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies 261
Introduction 262
Partial and Dynamic Reconfiguration 263
One-dimensional Dynamic and Partial Reconfigurable System Architecture 263
LUT Based Communication Primitives 264
Physically Realized Two-dimensional System Approach 266
Network on Chip 266
Router Base Modules for the On-line Placement 266
Switch for 2D Mesh Based NoC Approach 268
Switch Layout 268
Controlling the Switch 269
On Demand System Adaption 269
Physical on Line Routing of Communication Structures 269
Physical On-line Routing of Parameterizable Filter Modules 270
System Modelling 271
Tool Chain 273
Model Debugging 275
Problem 275
Debugging Flow 275
Interface and Architecture 276
Test 278
Conclusions 279
References 281
ReconOS: An Operating System for Dynamically Reconfigurable Hardware 284
Introduction 284
Related Work 285
Programming Model 286
Hardware Threads 288
Thread Creation and Termination 288
Run-Time System 289
Hardware Architecture 290
The Operating System Interface 290
Thread Supervision and Control 291
OS Call Relaying 292
Data Communication Routing 292
Hardware Multitasking 293
Software Architecture 293
Delegate Threads 294
Hardware Scheduler 294
Implementation 295
Target Platforms 295
Prototypes 295
ReconOS/eCos 296
ReconOS/Linux 298
Debugging and Monitoring 298
Experimental Measurements 299
Application Case Studies 301
Conclusion and Outlook 303
References 303
Part IV Applications 306
FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems 307
Introduction 307
Channel Codes 309
Convolutional Codes 310
Turbo Codes 310
LDPC Codes 311
Decoder Requirements 313
ASIP Design Methodologies 313
Architecture 314
General Considerations 314
Memory Concept 316
Pipeline 317
Dynamically Reconfigurable Channel Code Control 318
Instruction Set 320
ASIP Validation 322
Results 324
References 327
Dynamically Reconfigurable Systems for Wireless Sensor Networks 329
Introduction 329
Outline 330
Motivation and Background 330
Design of a Reconfigurable Function Unit 331
Functional Coverage of the RFU 332
The RFU Data Path 332
Dynamic Reconfiguration 334
Intra-task Reconfiguration 334
The Multi-context Configuration Table 334
Run Control via Tag-matching 336
Inter-task Reconfiguration 337
General System Architecture 338
Evaluation Results 339
Test Settings 340
Synthesis Results 340
Evaluation of Energy Efficiency 340
Reconfiguration Overhead 341
Comparison of Alternative Reconfiguration Mechanisms 341
Reconfiguration Power 342
Architecture Comparison 344
Prototyping of the Sensor Node System 345
Generalisation of the Results 346
Conclusion 346
References 347
DynaCORE-Dynamically Reconfigurable Coprocessor for Network Processors 349
Introduction 349
Network Processors 350
Requirements 351
System Architecture 352
Model 353
Principles of Theory 354
Modelling DynaCORE 354
Simulation 355
Runtime Adaptive Network-on-Chip 357
Architecture 358
Runtime Adaptation 359
Fault Tolerance 359
Reconfiguration Management 360
Basic Method 361
Optimised Approach 361
Technical Aspects 364
Evaluation 365
Summary 367
References 367
FlexPath NP-Flexible, Dynamically Reconfigurable Processing Paths in Network Processors 369
Introduction 369
FlexPath NP Concept 371
Application Dependent Path Decision 372
Load Dependent Path Decision 373
Formal Analysis 374
Simulative Exploration 375
FlexPath NP Architecture Evaluation 376
Load Balancing in FlexPath NP 377
FPGA Demonstrator 378
Architecture 378
Experiments 381
Demonstrator Setup 381
Single Data Plane CPU (Scenarios 1 and 2) 382
Two Data Plane CPUs (Scenarios 3 and 4) 383
AutoRoute (Scenario 5) 385
DynaCORE (Scenario 6) 386
Conclusion 386
References 387
AutoVision-Reconfigurable Hardware Acceleration for Video-Based Driver Assistance 389
Introduction 389
State of the Art & Related Work
Typical Scenario & Hardware Accelerators
AutoVision Architecture 394
The AddressEngine-A Pixel Processing Pipeline 395
Fast Dynamic Partial Reconfiguration 397
Motivation for Fast Reconfiguration 397
Inter Video Frame Reconfiguration 397
Intra Video Frame Reconfiguration 398
Bitstream Modification 398
Combitgen 398
Hardware Modification 400
ICAP Controller 400
Optimizing Throughput Through Modular Design 402
Bitstream Verification 403
Results 404
Performance of the Engines 405
Conclusion and Outlook 406
References 407
Procedures for Securing ECC Implementations Against Differential Power Analysis Using Reconfigurable Architectures 409
Introduction 409
Elliptic Curve Cryptography 410
Elliptic Curve Arithmetic 411
Finite Field Arithmetic 411
Karatsuba Multiplication 412
Multi-Segment-Karatsuba Multiplication 413
Enhanced Multi-Segment-Karatsuba Multiplication 414
Side Channel Attacks 415
Information Leaking of ECC Hardware Architectures 418
General Countermeasure Techniques 419
Countermeasure Through Reconfiguration 420
Securing ECC on Finite Field Arithmetic Level 421
Securing ECC on Elliptic Curve Arithmetic Level 423
DPA Experiments on Countermeasures 425
Resistance of the Secured eMSK-Multiplier 426
Conclusion and Future Work 427
References 428
Reconfigurable Controllers-A Mechatronic Systems Approach 430
Introduction 430
Design Methodology 434
Logical Controller Structure and Partitioning 434
Specification of Reconfigurable Controller Functionalities 436
Distributed Reconfiguration Control and Activation Strategies 437
Structure and Implementation 438
Structure and Components 439
Implementation and Target Hardware 441
Partial Reconfiguration Solution 442
Application 443
A Reconfigurable Controller for Piezo-Electric Actuators 443
Conclusion 447
References 448
Index 450