Low-Power Design of Nanometer FPGAs (eBook)

Front Cover 1
Title Page 4
Copyright Page 5
Dedication Page 6
Table of Contents 8
Author Bios 14
Chapter 1. FPGA Overview: Architecture and CAD 16
1.1 Introduction 17
1.2 FPGA Logic Resources Architecture 20
1.2.1 Altera Stratix IV Logic Resources 21
1.2.2 Xilinx Virtex-5 Logic Resources 22
1.2.3 Actel ProASIC3/IGLOO Logic Resources 23
1.2.4 Actel Axcelerator Logic Resources 24
1.3 FPGA Routing Resources Architecture 25
1.4 CAD for FPGAs 27
1.4.1 Logic Synthesis 27
1.4.2 Packing 28
1.4.3 Placement 29
1.4.4 Timing Analysis 31
1.4.5 Routing 31
1.5 Versatile Place and Route (VPR) CAD Tool 32
1.5.1 VPR Architectural Assumptions 32
1.5.2 Basic Logic Packing Algorithm: VPack 37
1.5.3 Timing-Driven Logic Block Packing: T-VPack 39
1.5.4 Placement: VPR 41
1.5.5 Routing: VPR 43
Chapter 2. Power Dissipation in Modern FPGAs 46
2.1 CMOS Technology Scaling Trends and Power Dissipation in VLSI Circuits 47
2.2 Dynamic Power in FPGAs 50
2.3 Leakage Power in FPGAs 50
2.3.1 CMOS Device Leakage Mechanisms 50
2.3.2 Current Situation of Leakage Power in Nanometer FPGAs 53
Chapter 3. Power Estimation in FPGAs 56
3.1 Introduction 57
3.2 Power Estimation in VLSI: An Overview 59
3.2.1 Simulation-Based Power Estimation Techniques 59
3.2.2 Probabilistic-Based Power Estimation Techniques 62
3.3 Commercial FPGA Power Estimation Techniques 65
3.3.1 Spreadsheet Power Estimation Tools 65
3.3.2 CAD Power Estimation Tools 66
3.4 A Survey of FPGA Power Estimation Techniques 68
3.4.1 Linear Regression-Based Power Modeling 69
3.4.2 Probabilistic FPGA Power Models 71
3.4.3 Look-up Table–Based FPGA Power Models 71
3.5 A Complete Analytical FPGA Power Model under Spatial Correlation 73
3.5.1 Spatial Correlation and Signal Probability Calculations 73
3.5.2 Exploration Phase: Locating Spatial Correlation 75
3.5.3 Signal Probabilities Calculation Algorithm under Spatial Correlation 76
3.5.4 Power Calculations Due to Glitches 80
3.5.5 Signal Probabilities and Power Dissipation 81
3.5.6 Results and Discussion 86
Chapter 4. Dynamic Power Reduction Techniques in FPGAs 100
4.1 Multiple Supply Voltages 101
4.1.1 Predefined Dual-VDD Dual-VTH FPGAs 102
4.1.2 Programmable Dual-VDD 107
4.1.3 Other Dual-VDD FPGA Techniques 112
4.2 Reducing Glitches in FPGAs 114
4.2.1 Glitch Power Reduction Using Delay Insertion 114
4.2.2 Multiphase Flip-Flop Insertion for Glitch Power Reduction in FPGAs 120
4.2.3 Negative Edge Flip-Flop Insertion for Glitch Power Reduction in FPGAs 130
4.2.4 Behavioral Synthesis with Flip-Flop Insertion for Glitch Power Reduction in FPGAs 132
4.3 CAD Techniques for Reducing Dynamic Power in FPGAs 137
4.3.1 Power Reduction Techniques during Technology Mapping 137
4.3.2 Power Reduction Techniques during Clustering 147
4.3.3 Power Reduction Techniques during Placement and Routing 149
Chapter 5. Leakage Power Reduction in FPGAs Using MTCMOS Techniques 154
5.1 Introduction 155
5.2 MTCMOS FPGA Architecture 158
5.3 Sleep Transistor Design and Discharge Current Processing 163
5.3.1 Sleep Transistor Sizing 163
5.3.2 Mutually Exclusive Discharge Current Processing 166
5.3.3 Logic-Based Discharge Current Processing 168
5.3.4 Topological Sorting and Discharge Current Addition 169
5.4 Activity Profile Generation 173
5.4.1 Connection-Based Activity Profile Generation Algorithm (CAP) 175
5.4.2 LAP Generation 181
5.5 Activity Packing Algorithms 189
5.5.1 AT-VPack 190
5.5.2 Force-Based Activity T-VPack (FAT-VPack) 192
5.5.3 Timing-Driven MTCMOS (T-MTCMOS) AT-VPack 193
5.6 Power Estimation 195
5.7 Results and Discussion 196
5.7.1 Experimental Setup 197
5.7.2 Algorithm Comparison 198
5.7.3 Impact of Activity Packing on Performance 201
5.7.4 Leakage Savings Breakdown 204
5.7.5 Impact of Utilization and ON Time on Leakage Savings 206
5.7.6 Impact of the Sleep Region Size 208
5.7.7 Scalability of the Proposed Algorithms with Technology Scaling 209
Chapter 6. Leakage Power Reduction in FPGAs Through Input Pin Reordering 210
6.1 Leakage Power and Input State Dependency in FPGAs 212
6.1.1 Subthreshold Leakage Current 212
6.1.2 Gate Leakage 215
6.1.3 Low-Leakage States in Pass-Transistor Multiplexers 216
6.1.4 Leakage Power in Inverters/Buffers 218
6.2 The Input Pin Reordering Algorithm 219
6.2.1 LPR Algorithm 220
6.2.2 Routing Switch Pin Reordering (RPR) Algorithm 225
6.3 Experimental Results 227
6.3.1 Pin Reordering and Performance 230
6.3.2 Pin Reordering and Technology Scaling 233
6.4 Conclusion 234
References 236
Index 252