Inside NAND Flash Memories (eBook)

Preface 6
Acknowledgements 8
Table of contents 10
1 Market and applications for NAND Flash memories 12
1.1 Introduction 12
1.2 Flash memory architectures 13
1.3 Multi-bit per cell storage 16
1.3.1 Memories scaling 16
1.3.2 Multi-level cell concept 16
1.3.3 NAND scaling 17
1.3.4 Capacity 18
1.3.5 Device characteristics 19
1.4 Market and applications 21
1.4.1 Removable portable storage 21
1.4.2 Embedded storage 21
1.4.3 Solid state drives 24
1.5 Market outlook 28
2 NAND overview: from memory to systems 30
2.1 Introduction 30
2.2 NAND memory 31
2.2.1 Array 31
2.2.2 Basic operations 33
Read 34
Program 35
Erase 36
2.2.3 Logic organization 38
2.2.4 Pinout 39
2.3 Command set 40
2.3.1 Read operation 40
2.3.2 Program operation 44
2.3.3 Erase operation 46
2.3.4 Synchronous operations 47
2.4 NAND-based systems 49
2.4.1 Memory controller 51
Wear leveling 52
Garbage collection 52
Bad block management 53
ECC 54
2.4.2 Multi-die systems 55
2.4.3 Die stacking 56
2.4.4 3D memories and XLC storage 61
References 63
3 Program and erase of NAND memory arrays 65
3.1 Floating gate cell physics 65
3.1.1 The ONO IPD floating gate cell 66
3.1.2 The band diagram of the floating gate cell 67
3.1.3 Capacitive cell model 68
3.2 Altering the stored charges 70
3.2.1 Fowler–Nordheim tunneling mechanism 70
3.2.2 Incremental step pulse programming ISPP 72
3.2.3 Interaction between cell parameters and ISPP 75
3.3 The NAND array 76
3.4 The program operation and its side effects in the NAND array 77
3.4.1 Self-boosted program inhibit SBPI 78
3.4.2 Capacitive model of the NAND string 80
3.4.3 Disturb effects 81
3.4.3.1 Program disturb 82
3.4.3.2 Pass disturb 83
3.4.3.3 Edge disturb 83
3.4.4 Advanced SBPI schemes 83
3.4.4.1 Local SBPI schemes 84
3.4.4.2 Asymmetric SBPI 85
3.5 The erase operation and the NAND array 87
3.5.1 Self-boosted erase inhibit SBEI 87
3.5.2 Erase disturb 87
3.6 Stochastic effects: Impact on cell distributions 88
3.6.1 Process variations 88
3.6.2 Floating gate cross-coupling 90
3.6.3 Injection statistics 92
3.6.4 Models for Cell–System Interaction 93
References 94
4 Reliability issues of NAND Flash memories 99
4.1 Introduction 99
4.2 Basic concepts 99
4.3 Basic reliability effects related to tunnel oxides 101
4.3.1 Endurance and intrinsic oxide degradation 101
4.3.2 Hot Hole Injection oxide degradation 103
4.3.3 Data retention 105
4.3.4 Overprogramming 107
4.3.5 General comments concerning oxide degradation 108
4.4 Disturbs related to memory architecture 109
4.5 Emerging reliability threats 111
4.5.1 Gate Induced Drain Leakage 111
4.5.2 Random Telegraph Noise 114
4.5.3 Charge injection statistics 117
4.5.4 Temperature instabilities 120
References 122
5 Charge trap NAND technologies 124
5.1 Introduction 124
5.2 Planar charge trap NAND 124
5.2.1 Stack description 124
5.2.2 Cell write mechanisms 126
Program 128
Erase 129
5.2.3 Stack options 130
5.2.4 Why charge trap memories? 133
5.2.5 Planar charge trap issues 134
5.3 3D charge trap memories 134
Acknowledgments 136
References 137
6 Control logic 139
6.1 Logic device view 139
6.2 Command interface 141
6.3 Test interface 145
6.4 Datapath 148
6.5 Microcontroller 151
6.6 ROM 158
6.7 RAM 160
6.8 Meta-language 161
References 166
7 NAND DDR interface 168
7.1 NAND Flash evolution: the need for increased bandwidth 168
7.1.1 Applications driving the NAND high speed interface evolution 169
7.1.2 Limitations of the asynchronous interface 170
7.1.3 How to improve the performance of NAND based systems 172
7.1.4 Adopting DDR protocol 173
7.1.5 High density systems: density, power and performance 176
7.2 Basic input output circuit design 179
7.2.1 I/O circuits for asynchronous NAND 179
7.2.2 Basic CMOS output buffer design 180
7.2.3 Driving high capacitive loads and noise: slew rate control 182
7.2.4 Simultaneous Switching Noise (SSN) 184
7.3 High speed NAND I/O design 186
7.3.1 High speed output buffer circuits 187
7.3.2 Double data rate OCD 188
7.3.3 OCD linearity: push–pull and open-drain configurations 189
7.3.4 Slew rate control and bandwidth 192
7.3.5 Voltage domain change: level shifting 194
7.3.6 Jitter sources and duty cycle distortion 195
7.3.7 ESD 196
Input and output ESD protections 198
7.3.8 Layout 198
7.3.9 I/O capacitance problem 200
References 202
8 Sensing circuits 204
8.1 Introduction 204
8.2 Reading techniques using the bitline capacitor 207
8.2.1 Interleaving architecture 216
8.2.2 Interleaving architecture: page buffer core design 219
8.3 Reading techniques with time-constant bitline biasing 225
8.3.1 All BitLine (ABL) architecture 227
8.3.2 ABL architecture: sensing design 230
8.4 ABL versus interleaving architecture 232
References 238
9 Parasitic effects and verify circuits 241
9.1 Background pattern dependency (BPD) 241
9.2. Reading techniques for negative sensing 244
9.2.1 Conventional negative verify 245
9.2.2 Absolute negative sensing 248
9.2.3 Current sensing 254
9.2.4 Source line read for ABL sensing 256
9.3 Source line bias error 258
9.3.1 Sensing with source line bias compensation 262
9.3.2 Multi-pass sensing 264
References 266
10 MLC storage 267
10.1 MLC coding and programming algorithms 267
10.1.1 Full-sequence programming 269
10.1.2 Floating gate coupling reduction 271
10.2 MLC sensing circuit 274
10.2.1 Read 274
10.2.2 Cache read 277
10.2.3 MLC program/verify operations 282
10.2.4 Check circuits 289
10.2.5 Coarse and fine programming 291
10.3 Data-load 295
10.3.1 Data-load 1 295
10.3.3 Data-load 3 300
10.4 Moving read voltages 302
References 303
11 Charge pumps, voltage regulators and HV switches 305
11.1 Charge pumps 305
11.2 Read regulator 309
11.3 Double-supply voltage regulator 314
11.4 Voltage references 321
11.5 Internal supply voltage regulator 324
References 332
12 High voltage overview 334
12.1 Program algorithm 334
12.2 Erase algorithm 338
12.3 HV system 342
12.4 Wordline decoder 346
12.5 Hierarchical GWL decoder 351
References 356
13 Redundancy 357
13.1 Redundancy concept 357
13.2 NAND architecture and redundancy 358
13.3 Process data failure analysis and redundancy requirements 362
13.3.1 Failure analysis concept 363
13.3.2 EWS substitution 366
13.4 Redundancy architectures 369
13.4.1 Realtime substitution 369
13.4.2 Software substitution 375
13.5 Fuse ROM 387
13.6 NAND block as OTP for redundancy data concept 392
References 395
14 Error correction codes 397
14.1 Introduction 397
14.2 Mathematical background 398
14.2.1 Block codes 399
14.2.2 Convolutional codes 402
14.3 BCH codes 405
14.3.1 Encoding 406
14.3.2 Decoding 407
14.4 Reed–Solomon codes 410
14.5 BCH versus Reed–Solomon 411
14.6 Parallel BCH 413
14.7 Low-Density Parity-Check (LDPC) code 417
14.7.1 LDPC code decoding algorithm 418
14.7.2 LDPC code construction and encoder/decoder design 420
14.7.3 QC-LDPC code performance evaluation 423
References 425
15 NAND design for testability and testing 427
15.1 NAND architecture and testing 427
15.1.1 Array testing 429
15.1.2 High voltage pumps testing 430
15.1.3 Read circuitry testing 431
15.2 NAND Flash memory testing introduction 432
15.2.1 Test phases: first silicon, ramp-up, production 432
15.2.2 NAND Flash test flow introduction 433
Wafer level flow 434
Back-end flow 434
Burn-in 435
15.2.3 Test flow and test time optimization 437
15.2.4 KGD testing 439
15.2.5 BAD Blocks Management 439
15.3 NAND DFT 440
15.3.1 Special test pads 441
15.3.2 Low Pin Count Testing (LPCT) 443
15.3.3 Voltage regulators and trimming 444
15.3.4 Fuse ROM 446
15.3.5 OTP Blocks 446
15.3.6 Test interface 447
15.3.7 Microcontroller as Built In Self Test (BIST) hardware 447
15.3.8 Fail counter 447
15.4 Fundamental NAND test modes 448
15.4.1 Parallel tests 449
Parallel wordline Program 449
Parallel erase 449
Parallel read 450
Parallel program of array and redundancy 450
15.4.2 Margin read 450
15.4.3 Data fail compression 450
15.4.4 Internal Vth search 451
15.4.5 ROM, RAM, Fuse ROM testing 452
15.4.6 Internal clock measurement 452
15.4.7 Tests for defect detection and yield enhancement 453
Shorts among bit lines detection 454
Bit lines opens, string open 454
Shorts between wordlines 454
15.4.8 Stress modes 455
References 456
16 XLC storage 458
16.1 Introduction 458
16.2 VTH distribution width 460
16.3 8LC 462
16.3.1 Program sequence 462
16.3.2 Program: circuits and cache operation 467
16.3.3 Read: circuits and cache operation 472
16.4 16LC 474
16.4.1 Three rounds re-programming sequence 478
16.4.2 Sequential sensing 480
References 485
17 Flash cards 486
17.1 Introduction 486
17.2 Memory card architecture and assembly 487
17.3 Memory card specifications 489
17.3.1 Pinout 489
17.3.2 Commands and responses 489
17.3.3 Registers 493
17.4 Flash translation layer 495
17.5 Cryptography 500
17.6 Execute in place 502
17.7 Managed memory 503
17.7.1 Multibit and shrink technology issues 504
Read disturb 505
Pass disturb 506
Program disturb 507
Trapping and Detrapping 507
Coupling 508
17.7.2 Microcontroller solutions 509
17.7.3 Flexible solution 513
References 515
18 Low power 3D-integrated SSD 517
18.1 Introduction 517
18.2 Analysis of SSD performance 518
18.3 Selective bit-line precharge scheme 522
18.4 Advanced source-line program 525
18.5 Intelligent interleaving 527
18.6 Sector size optimization 529
18.7 Adaptive program-voltage generator for 3D-SSD 531
18.8 Conclusions 537
References 537
19 Radiation effects on NAND Flash memories 539
19.1 Introduction to radiation effects in CMOS circuits 540
19.1.1 Environments 540
19.1.1.1 Terrestrial environment 540
19.1.1.2 Space 541
19.1.2 Overview of radiation effects 542
19.1.2.1 Radiation–matter interaction 542
19.1.2.2 Categories of radiation effects 544
19.1.3 Total ionizing dose effects 545
19.1.3.1 Basic mechanisms 545
19.1.3.2 Effects on MOSFETs 546
19.1.3.3 Scaling 547
19.1.4 Single event effects 548
19.2 Radiation effects on NAND Flash memories 550
19.2.1 Total ionizing dose effects 551
19.2.1.1 Floating gate cells 552
19.2.1.2 Charge pumps 553
19.2.1.3 Decoders 555
19.2.2 Single event effects 556
19.2.2.1 Floating gate cells and page buffer 556
19.2.2.2 Single event functional interruptions 557
19.2.2.3 Power supply current spikes 558
19.2.2.4 Overall cross section 559
19.3 Radiation effects on floating gate cells 560
19.3.1 Total ionizing dose 560
19.3.2 Single event effects 563
19.3.3 Long-term effects 565
19.3.4 Atmospheric neutrons 566
19.4 Conclusions 567
References 568
About the authors 574
Index 575