Low-Power CMOS Design

Anantha P. Chandrakasan received the B.S, M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, in 1989, 1990, and 1994 respectively. Since September 1994, he has been with the Massachusetts Institute of Technology, Cambridge.                                                 Chandrakasan leads the MIT Energy-Efficient Circuits and Systems Group, whose research projects have addressed security hardware, energy harvesting, and wireless charging for the internet of things; energy-efficient circuits and systems for multimedia processing; and platforms for ultra-low-power biomedical electronics. 

Preface. OVERVIEW.

Low Power Microelectronics: Retrospect and Prospect (J. Meindl).

Micropower IC (E. Vittoz).

Low-Power CMOS Digital Design (A. Chandrakasan, et al.).

CMOS Scaling for High Performance and Low-Power—The Next Ten Years (B. Davari, et al.).

LOW VOLTAGE TECHNOLOGIES AND CIRCUITS.

Low-Voltage Technologies and Circuits (T. Kuroda & T. Sakurai).

Threshold Voltage Scaling and Control.

Ion-Implanted Complementary MOS Transistors in Low-Voltage Circuits (R. Swanson & J. Meindl).

Trading Speed for Low Power by Choice of Supply and Threshold Voltages (D. Liu & C. Svensson).

Limitation of CMOS Supply-Voltage Scaling by MOSFET Threshold-Voltage Variation (S. Sun & P. Tsui).

Multiple Threshold CMOS (MTCMOS).

1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold Voltage CMOS (S. Mutoh, et al.).

A 1-V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Application (S. Mutoh, et al.).

Substrate Bias Controlled Variable Threshold CMOS.

50% Active-Power Saving Without Speed Degradation Using Standby Power Reduction (SPR) Circuit (K. Seta, et al.).

A 0.9V, 150MHz 10mW 4mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme (T. Kuroda, et al.).

Silicon-on-Insulator Based Technologies.

SOI CMOS for Low Power Systems (D. Antoniadis).

Back Gated CMOS on SOIAS for Dynamic Threshold Voltage Control (I. Yang, et al.).

Design of Low Power CMOS/SOI Devices and Circuits for Memory and Signal Processing Applications (L. Thon & G. Shahidi).

A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Operation (F. Assaderaghi, et al.).

A 0.5V SIMOX-MTCMOS Circuit with 200ps Logic Gate (T. Douseki, et al.).

EFFICIENT DC-DC CONVERSION AND ADAPTIVE POWER SUPPLY SYSTEMS.

Efficient Low Voltage DC-DC Converter Design.

A Low-Voltage CMOS DC-DC Converter for a Portable Battery-Operated System (A. Stratakos, et al.).

Ultra Low-Power Control Circuits for PWM Converters (A. Dancy & A. Chandrakasan).

Adaptive Power Supply Systems.

A Voltage Reduction Technique for Battery Operated Systems (V. von Kaenel, et al.).

Automatic Adjustment of Threshold and Supply Voltage for Minimum Power Consumption in CMOS Digital Circuits (V. von Kaenel, et al.).

Low-Power Operation Using Self-Timed Circuits and Adaptive Scaling of the Supply Voltage (L. Nielsen, et al.).

A Low-Power Switching Power Supply for Self-Clocked Systems (G. Wei & M. Horowitz).

Variable-Voltage Digital-Signal Processing (V. Gutnik & A. Chandrakasan).

Scheduling for Reduced CPU Energy (M. Weiser, et al.).

CIRCUIT AND LOGIC STYLES.

Conventional Circuit and Logic Styles.

Silicon-Gate CMOS Frequency Divider for the Electronic Wrist Watch (E. Vittoz, et al.).

CODYMOS Frequency Dividers Achieve Low Power Consumption and High Frequency (H. Oguey & E. Vittoz).

Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits (H. Veendrick).

A 3.8ns CMOS 16x16 Multiplier Using Complementary Pass Transistor Logic (K. Yano, et al.).

A High-Speed, Low-Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications (A. Parameswar, et al.).

Static Power Driven Voltage Scaling and Delay Driven Buffer Sizing in Mixed Swing QuadRail for Sub-IV I/O Swings (R. Krishnamurthy, et al.).

The Power Consumption of CMOS Adders and Multiliers (T. Callaway & E. Swartzlander, Jr.).

Delay Balanced Multipliers for Low Power/Low Voltage DSP Core (T. Sakuta, et al.).

Asynchronous Does Not Imply Low Power, But, ... (K. Van Berkel, et al.).

Latches and Flip-Flops for Low-Power Systems (C. Svensson & J. Yuan).

Adiabatic Logic Circuits.

Zig-Zag Path to Understanding (R. Landauer).

A Low-Power Multiphase Circuit Technique (B. Watkins).

Asymptotically Zero Energy Split-Level Charge Recovery Logic (S. Younis & T. Knight).

Low Power Ditigal Systems Based on Adiabatic Switching Principles (W. Athas, et al.).

Adiabatic Dynamic Logic (A. Dickinson & J. Denker).

DRIVING INTERCONNECT.

Sub-1-V Swin Internal Bus Architecture for Future Low-Power ULSIs (Y. Nakagome, et al.).

Data-Dependent Logic Swing Internal Bus Architecture for Ultra Low-Power LSIs (M. Hiraki, et al.).

An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultra-High Data Rate ULSIs (H. Yamauchi, et al.).

Bus-Invert Coding for Low Power I/O (M. Stan & W. Burleson).

A Sub-CV2 Pad Driver with 10 ns Transition Time (L. Svensson, et al.).

MEMORY CIRCUITS.

Reviews and Prospects of Low-Power Memory Circuits (K. Itoh).

DRAM.

Trends in Low-Power RAM Circuit Technologies (K. Itoh, et al.).

Standby/Active Mode Logic for Sub-1V Operating ULSI Memory (D. Takashima, et al.).

A Charge Recycle Refresh for Gb-scale DRAM's in File Application (T. Kawahara, et al.).

SRAM.

A 1-V 1-Mb SRAM for Portable Equipment (H. Morimura & N. Shibata).

A Single Bitline Cross-Point Cell Activation (SCPA) Architecture for Ultra-Low-Power SRAMs (M. Ukita, et al.).

Techniques to Reduce Power in Fast Wide Memories (B. Amrutur & M. Horowitz).

A 2-ns, 5-mW, Synchronous-Powered Static-Circuit Associative TLB (H. Higuchi, et al.).

Driving Source-Line (DSL) Cell Architecture for Sub-1-V High Speed Low Power Applications (H. Mizuno & T Nagano).

PORTABLE TERMINAL ELECTRONICS.

General Purpose Processor Design.

Energy Dissipation in General Purpose Microprocessors (R. Gonzalez & M. Horowitz).

Energy Efficient CMOS Microprocessor Design (T. Burd & R. Brodersen).

A 160MHz 32b 0.5W CMOS RISC Microprocessor (J. Montanaro, et al.).

A 320MHz, 1.5mW @ 1.35V CMOS PLL for Microprocessor Clock Generation (V. Von Kaenel, et al.).

Dedicated and Programmable Digital Signal Processors.

A Low-Power Chipset for a Portable Multimedia I/O Terminal (A. Chandrakasan, et al.).

A Portable Real-Time Video Decoder for Wireless Communication (T. Meng, et al.).

Low Power Design of Memory Intensive Functions (D. Lidsky & J. Rabaey).

A 16b Low-Power Digital Signal Processor (K. Ueda, et al.).

A 1.8V 36mW DSP for the Half-Rate Speech CODEC (T. Shiraishi, et al.).

Design of a 1-V Programmable DSP for Wireless Communication (P. Landman, et al.).

Stage-Skip Pipeline: A Low Power Processor Architecture Using a Decoded Instruction Buffer (M. Hiraki, et al.).

COMPUTER AIDED DESIGN TOOLS.

Power Analysis Techniques.

Transition Density: A New Measure of Activity in Digital Circuits (E. Najm).

Estimation of Average Switching Activity in Combinational and Sequential Circuits (A. Ghosh, et al.).

Power Estimation for Sequential Logic Circuits (C. Tsui, et al.).

A Monte Carlo Approach for Power Estimation (R. Burch, et al.).

Stratified Random Sampling for Power Estimation (C.-S. Ding, et al.).

A Survey of High-Level Power Estimation Techniques (P. Landman).

Activity-Sensitive Architectural Power Analysis (P. Landman & J. Rabaey).

Power Analysis of Embedded Software: A First Step Towards Software Power Minimization (V. Tiwari, et al.).

Power Optimization Techniques.

Technology Mapping for Low Power (V. Tiwari, et al.).

POSE: Power Optimization and Synthesis Environment (S. Iman & M. Pedram).

Transformation and Synthesis of FSMs fo Low-Power Gated-Clock Implementation (L. Benini & G. De Micheli).

Precomputation-Based Sequential Logic Optimization for Low Power (M. Alidina, et al.).

Glitch Analysis and Reduction in Register Transfer Level Power Optimization (A. Raghunathan, et al.).

Exploiting Locality for Low-Power Design (R. Mehra, et al.).

HYPER-LP: A System for Power Minimization Using Architectural Transformations (A. Chandrakasan, et al.).

Variable Voltage Scheduling (S. Raje & M. Sarrafzadeh).

System)-Level Transformations for Low Power Data Transfer and Storage (F. Catthoor, et al.).

Author Index.

Index.