Formal Techniques in Real-Time and Fault-Tolerant Systems
Springer Berlin (Verlag)
978-3-540-44165-6 (ISBN)
Invited Tutorials.- UppaaL Implementation Secrets.- Software Hazard and Safety Analysis.- Invited Papers.- Real-Time Operating Systems: Problems and Novel Solutions.- Real-Time UML.- Eager Class Initialization for Java.- Applications of Formal Methods in Biology.- An Overview of Formal Verification for the Time-Triggered Architecture.- Scheduler Modeling Based on the Controller Synthesis Paradigm.- Synthesis and Scheduling.- Component-Based Synthesis of Dependable Embedded Software.- From the Specification to the Scheduling of Time-Dependent Systems.- On Control with Bounded Computational Resources.- Timed Automata I.- Decidability of Safety Properties of Timed Multiset Rewriting.- Extending Timed Automaton and Real-Time Logic to Many-Valued Reasoning.- Fault Diagnosis for Timed Automata.- Bounded Model Checking.- Verification of Timed Automata via Satisfiability Checking.- Take It NP-Easy: Bounded Model Construction for Duration Calculus.- Towards Bounded Model Checking for the Universal Fragment of TCTL.- Verification and Conformance Testing.- A Typed Interrupt Calculus.- Parametric Verification of a Group Membership Algorithm.- A Method for Testing the Conformance of Real Time Systems.- UML Models and Model Checking.- A Probabilistic Extension of UML Statecharts.- Eliminating Queues from RT UML Model Representations.- Model Checking Timed UML State Machines and Collaborations.- Timed Automata II.- Partial Order Path Technique for Checking Parallel Timed Automata.- Constructing Test Automata from Graphical Real-Time Requirements.
Erscheint lt. Verlag | 28.8.2002 |
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Reihe/Serie | Lecture Notes in Computer Science |
Zusatzinfo | X, 462 p. |
Verlagsort | Berlin |
Sprache | englisch |
Maße | 155 x 235 mm |
Gewicht | 658 g |
Themenwelt | Mathematik / Informatik ► Informatik ► Programmiersprachen / -werkzeuge |
Informatik ► Theorie / Studium ► Compilerbau | |
Schlagworte | algorithms • Architecture • Automata • Erfüllbarkeitsproblem der Aussagenlogik • Formal Verification • Hardcover, Softcover / Informatik, EDV/Programmiersprachen • HC/Informatik, EDV/Informatik • HC/Informatik, EDV/Programmiersprachen • Interrupt • Logic • operating system • Scheduling |
ISBN-10 | 3-540-44165-4 / 3540441654 |
ISBN-13 | 978-3-540-44165-6 / 9783540441656 |
Zustand | Neuware |
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