System on Chip Design Languages

HDL Standardization.- 1. VHDL-2001: What’s new.- 2. Verilog-2001 Behavioral and Synthesis Enhancements.- 3. Advanced ASIC Sign-off Features of IEEE 1076.4-2000 and Standards Updates to Verilog and SDF.- Analog System Modeling and Design.- 4. VHDL-AMS model of a synchronous oscillator including phase noise.- 5. AnalogSL: A C++ Library for Modeling analog power drivers.- 6. Modeling micro-mechanical structures for system simulations.- 7. A Comparison of Mixed-Signal Modeling Approaches.- 8. A unified IP Design Platform for extremely flexible High Performance RF and AMS Macros using Standard Design Tools.- 9. Analogue Filter Synthesis from VHDL-AMS.- System Design Experiences.- 10. Using GNU Make to Automate the Recompile of VHDL SoC Designs.- 11. Wild Blue Yonder: Experiences in Designing an FPGA with State Machines for a Modern Fighter Jet, Using VHDL and DesignBook.- 12. Analysis of Modeling and Simulation Capabilities in SystemC and Ocapi using a Video Filter Design.- 13. The Guidelines and JPEG Encoder Study Case of System-Level Architecture Exploration Using the SpecC Methodology.- 14. Provision and Integration of EDA Web-Services using WSDL-based Markup.- System Verification.- 15. A Mixed C/Verilog Dual-Platform Simulator.- 16. Assertions Targeting a Diverse Set of Verification Tools.- 17. Predicting the Performance of SoC Verification Technologies.- System Specification.- 18. Aspects of object-oriented hardware modeling with SystemC-Plus.- 19. UML for system-level design.- 20. Open PROMOL: An Experimental Language for Target Program Modification.- 21. A system benchmark specification experiment with Esterel/C.- Real-Time Modeling.- 22. Modeling of real-time embedded systems by using SDL.- 23. A framework for specification and verification of timing constraints.-24. A general approach to modeling system-level timing constraints.