Quantifying and Exploring the Gap Between FPGAs and ASICs (eBook)

Preface 5
Contents 6
Acronyms 9
Introduction 10
Measuring the FPGA to ASIC Gap 11
Navigating the Gap 12
Organization 13
Background 14
FPGA Architecture 14
Logic Block Architecture 14
Logic Block Architecture of the Altera Stratix II 16
Routing Architecture 18
Heterogeneity 21
FPGA Circuit Design 22
FPGA Transistor Sizing 25
FPGA Assessment Methodology 26
FPGA CAD Flow 26
Area Model 27
Performance Measurement 29
Automated Transistor Sizing 29
Static Transistor Sizing 30
Dynamic Sizing 32
Hybrid Approaches to Sizing 32
FPGA-Specific Sizing 33
FPGA to ASIC Gap 33
Measuring the Gap 36
Comparison Methodology 37
Benchmark Circuit Selection 37
FPGA CAD Flow 40
ASIC CAD Flow 41
ASIC Synthesis 41
ASIC Placement and Routing 44
Extraction and Timing Analysis 45
Comparison Metrics 45
Area 45
Delay 46
Power 46
Dynamic and Static Power Measurement 47
Dynamic and Static Power Comparison Methodology 48
Measurement Results 48
Area 49
Approximate Bounds 52
Impact of Benchmark Size on FPGA Area Measurements 54
Other Considerations 56
Delay 58
Speed Grades 62
Retiming and Heterogeneous Blocks 63
Dynamic Power Consumption 64
Other Considerations 67
Static Power Consumption 67
Summary 70
Automated Transistor Sizing for FPGAs 72
Uniqueness of FPGA Transistor Sizing Problem 73
Programmability 73
Repetition 73
Optimization Tool Inputs 74
Logical Architecture Parameters 74
Electrical Architecture Parameters 75
Optimization Objective 76
Optimization Metrics 77
Area Model 77
Performance Modelling 80
Optimization Algorithm 82
Phase 1: Switch-Level Transistor Models 83
Switch-Level Transistor Models 83
TILOS-based algorithm 86
Termination Criteria 87
Phase 2: Sizing with Accurate Models 88
Parameter Grouping 90
Parameter Ordering 91
Quality of Results 91
Comparison with Past Routing Optimizations 91
Comparison with Past Logic Block Optimization 93
Comparison to Exhaustive Search 98
Optimizer Run Time 99
Summary 99
Navigating the Gap Using Architecture and Process Technology Scaling 100
Area and Performance Measurement Methodology 101
Performance Measurement 101
Area Measurement 103
Impact of Logical Architectures on Area and Performance 104
Impact of Process Technology Scaling on Area and Performance 107
Summary 110
Navigating the Gap using Transistor Sizing 112
Transistor-Sizing Trade-offs 113
Definition of ``Interesting'' Trade-offs 115
Trade-Offs with Transistor Sizing and Architecture 118
Impact of Elasticity Threshold Factor 120
Logical Architecture Trade-offs 121
LUT Size 122
Cluster Size 123
Segment Length 124
Circuit Structure Trade-offs 124
Buffer Positioning 125
Multiplexer Implementation 127
General Multiplexer Design Analysis 127
Area--Delay Trade-Offs Using Varied Multiplexer Designs 129
Trade-offs and the Gap 131
Comparison with Commercial Families 133
Summary 134
Conclusions and Future Work 135
Knowledge Gained 135
Future Potential Research Directions 136
Measuring the Gap 136
Navigating the Gap 138
Concluding Remarks 139
FPGA to ASIC Comparison Details 140
Benchmark Information 140
FPGA to ASIC Comparison Data 140
Representative Delay Weighting 147
Benchmark Statistics 147
LUT Usage 148
Representative Delay Weights 150
Multiplexer Implementations 153
Multiplexer Designs 153
Evaluation of Multiplexer Designs 155
Architectures Used for Area and Delay Range Investigation 160
Logical Architecture to Transistor Sizing Process 163
Index 181