Creating Assertion-Based IP - Harry D. Foster, Adam C. Krolnik

Creating Assertion-Based IP

Buch | Softcover
318 Seiten
2010 | 1st ed. Softcover of orig. ed. 2008
Springer-Verlag New York Inc.
978-1-4419-4218-0 (ISBN)
117,69 inkl. MwSt
This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. It demonstrates a systematic process for formal specification and formal testplanning and is the first book published on this subject.
Assertion-based IP is much more than a comprehensive set of related assertions. It is a full-fledged reusable and configurable transaction-level verification component, which is used to detect both interesting and incorrect behaviors. Upon detecting interesting or incorrect behavior, the assertion-based IP alerts other verification components within a simulation environment, which are responsible for taking appropriate action. The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user’s existing verification environment, in other words the testbench infrastructure.





The guiding principles promoted in this book when creating an assertion-based IP monitor are:








modularity—assertion-based IP should have a clear separation between detection and action


clarity—assertion-based IP should be written initially focusing on capturing intent (versus optimizations)








A unique feature of this book is the fully worked out, detailed examples. The concepts presented in the book are drawn from the authors’ experience developing assertion-based IP, as well as general assertion-based techniques. Creating Assertion-Based IP is an important resource for design and verification engineers.


From the Foreword:





Creating Assertion-Based IP "…reduces to process the creation of one of the most valuable kinds of VIP: assertion-based VIP…This book will serve as a valuable reference for years to come."

Andrew Piziali, Sr. Design Verification Engineer
Co-Author, ESL Design and Verification: A Prescription for Electronic System Level Methodology
Author, Functional Verification Coverage Measurement and Analysis

Definitions and Terminology.- The Process.- Bus-Based Design Example.- Interfaces.- Arbiters.- Controllers.- Datapath.

Erscheint lt. Verlag 19.11.2010
Reihe/Serie Series on Integrated Circuits and Systems
Zusatzinfo XVIII, 318 p.
Verlagsort New York, NY
Sprache englisch
Maße 155 x 235 mm
Themenwelt Informatik Weitere Themen CAD-Programme
Technik Elektrotechnik / Energietechnik
ISBN-10 1-4419-4218-1 / 1441942181
ISBN-13 978-1-4419-4218-0 / 9781441942180
Zustand Neuware
Haben Sie eine Frage zum Produkt?
Mehr entdecken
aus dem Bereich
Band 1: Produktion

von Thomas Bauernhansl

Buch | Hardcover (2024)
Springer Vieweg (Verlag)
99,99
Einführung in die Geometrische Produktspezifikation

von Daniel Brabec; Ludwig Reißler; Andreas Stenzel

Buch | Softcover (2023)
Europa-Lehrmittel (Verlag)
20,70