3D Integration for NoC-based SoC Architectures (eBook)

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2010 | 2011
X, 278 Seiten
Springer New York (Verlag)
978-1-4419-7618-5 (ISBN)

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This book presents the research challenges that are due to the introduction of the 3rd dimension in chips for researchers and covers the whole architectural design approach for 3D-SoCs. Nowadays the 3D-Integration technologies, 3D-Design techniques, and 3D-Architectures are emerging as interesting, truly hot, broad topics. The present book gathers the recent advances in the whole domain by renowned experts in the field to build a comprehensive and consistent book around the hot topics of three-dimensional architectures and micro-architectures. This book includes contributions from high level international teams working in this field.
This book presents the research challenges that are due to the introduction of the 3rd dimension in chips for researchers and covers the whole architectural design approach for 3D-SoCs. Nowadays the 3D-Integration technologies, 3D-Design techniques, and 3D-Architectures are emerging as interesting, truly hot, broad topics. The present book gathers the recent advances in the whole domain by renowned experts in the field to build a comprehensive and consistent book around the hot topics of three-dimensional architectures and micro-architectures. This book includes contributions from high level international teams working in this field.

Preface 5
Contents 7
Contributors 9
Part I 3DI Promises and Challenges 11
Three-Dimensional Integration of Integrated Circuits—an Introduction 12
1.1 Background and Introduction 12
1.2 Motivations and Drivers 13
1.2.1 Sustainable IC Performance Growth 13
1.2.2 Show-Stoppers and 3-D Integration as a Remedy 15
1.2.2.1 Transistor Scaling Barriers 15
1.2.2.2 On-Chip Interconnect 16
1.2.2.3 Off-Chip Interconnect (Memory Bandwidth Gap) 17
1.3 Options of 3D IC 19
1.3.1 System Integration Landscape 19
1.3.2 Classification 19
1.3.3 Monolithic Approaches 20
1.3.4 Assembly Approaches 21
1.4 Technology Platforms and Strategies 25
1.4.1 Through Silicon Via 25
1.4.2 Cu–Cu Permanent Bonding 26
1.4.2.1 Wafer Preparation and Bonding Procedures 27
1.4.2.2 Bonding Mechanism 27
1.4.2.3 Surface Oxide 28
1.4.2.4 Process Parameters 28
1.4.2.5 Observation of Interfacial Voids 29
1.4.2.6 Non-Blanket Cu Bonding 30
1.4.2.7 Low Temperature Cu Bonding 31
1.5 Applications, Status and Outlook 32
References 34
The Promises and Limitations of 3-D Integration 36
2.1 Introduction 36
2.2 Computational Efficiency of Silicon 38
2.2.1 Computation 38
2.2.2 Adding Memory and Communication 39
2.2.3 Effective Computational Efficiency 40
2.2.4 Effective Computational Density 41
2.3 Technology Parameter Scaling 43
2.3.1 Planar 2-D Wire Models 43
2.3.2 3-D TSV Interconnect Models 43
2.3.3 Logical Operation and DRAM Scaling 44
2.4 ECE Trends and Dependencies 45
2.4.1 Distributed Versus Central Memory 45
2.4.2 On-chip Versus Off-chip Memory 46
2.4.3 Size Constrained System 48
2.4.4 Power and Frequency Constrained Systems 50
2.5 Conclusion 51
Part II Technology and Circuit Design 54
Testing 3D Stacked ICs Containing Through-Silicon Vias 55
3.1 Introduction 55
3.2 3D-SICs Based on TSV Technology 56
3.3 3D Test Flows 60
3.3.1 Prior Art in Test Flows 60
3.3.2 Test Flows for 3D-SICs 61
3.3.3 Pre-Bond Testing for W2W Stacking 63
3.4 Modular Testing 64
3.5 3D Test Contents 66
3.5.1 New Intra-Die Defects 66
3.5.2 Test of TSV-Based Interconnects 67
3.6 3D Wafer Test Challenges 69
3.6.1 Pre-Bond Wafer Test Access 69
3.6.2 Post-Bond Wafer Handling 73
3.7 3D On-Chip DfT Architecture 73
3.7.1 Hierarchical DfT Requirements 73
3.7.2 Simplified Example DfT Architecture 74
3.7.3 Advanced DfT Techniques and Test Resource Partitioning 77
3.8 Conclusion 78
Design and Computer Aided Design of 3DIC 83
4.1 Introduction 83
4.2 Technology Selection 83
4.2.1 What Am I Stacking (Fig. 4.1)? 83
4.2.2 Do I Need Through Silicon Vias (Fig. 4.3)? 85
4.2.3 Through Silicon Via (TSV) Technology 85
4.3 3D Specific Optimizations 87
4.3.1 Example of 3D Specific Optimized Design 88
4.4 3D Design and CAD 91
4.5 Outstanding Issues in 3D Design 93
4.5.1 Cost Management 93
4.5.2 Computer Aided Design 94
4.5.3 Thermal Design and Analysis 94
4.5.4 Test and Design for Test 94
4.6 Conclusions 95
Physical Analysis of NoC Topologies for 3-D Integrated Systems 97
5.1 Introduction 97
5.2 Three-Dimensional On-Chip Network Topologies 98
5.3 Timing and Power Model for 3-D NoCs 100
5.3.1 Latency Model for 3-D NoC 100
5.3.2 Power Consumption Model for 3-D NoC 105
5.4 Thermal-Aware Analysis Methodology 106
5.5 Latency, Power, and Temperature Tradeoffs in 3-D NoC Topologies 110
5.5.1 Latency of 3-D NoCs 111
5.5.2 Power Dissipation of 3-D NoCs 113
5.5.3 Temperature in 3-D NoCs 116
5.6 Summary 119
Three-Dimensional Networks-on-Chip: Performance Evaluation 123
6.1 Introduction 123
6.2 3D NoC Architectures 125
6.2.1 Mesh-Based Networks 125
6.2.2 Tree-Based Networks 128
6.3 Performance Evaluation 128
6.3.1 Performance Metrics 128
6.3.2 Performance Analysis of 3D Mesh-Based NoCs 130
6.3.3 Performance Analysis of 3D Tree-Based NoCs 132
6.3.4 Simulation Methodology 133
6.3.5 Experimental Results for Mesh-Based Networks 135
6.3.6 Experimental Results for Tree-Based Networks 138
6.3.7 Effects of Traffic Localization 141
6.3.8 Effects of Wire Delay on Latency and Bandwidth 143
6.3.9 Network Aspect Ratio 144
6.3.10 Multi-Layer IPs 146
6.4 Heat Dissipation Profile of 3D NoCs 147
6.4.1 Temperature Analysis 147
6.4.2 The Relationship Between Temperature and Energy 148
6.4.3 Simulation Methodology 148
6.4.4 Experimental Results 149
6.5 Conclusion 151
Part III System and Architecture Design 154
Asynchronous 3D-NoCs Making Use of Serialized Vertical Links 155
7.1 Introduction 155
7.2 3D-Integration Technology 156
7.2.1 TSV Technology Challenges 157
7.3 NoC and 3D-Design Contribution 158
7.4 Asynchronous Circuit Exploitation 160
7.5 Serialized Vertical Links 163
7.5.1 Implementation 165
7.6 Conclusion 170
Design of Application-Specific 3D Networks-on-Chip Architectures 172
8.1 Introduction 172
8.2 Related Work 174
8.3 Design Flow 175
8.3.1 Floorplanning 175
8.3.2 3D Networks-on-Chip Synthesis 176
8.3.3 NoC Objectives and Constraints 176
8.3.4 NoC Design Parameters 177
8.3.5 Detailed Design 178
8.4 Problem Description and Formulation 178
8.4.1 Problem Description 178
8.4.2 Problem Formulation 179
8.5 3D Design Models 180
8.5.1 3D Interconnect Modelling 180
8.5.2 Modelling Routers 182
8.6 Design Algorithms 183
8.6.1 Initial Network Construction 183
8.6.2 Flow Ripup and Rerouting 185
8.6.3 Router Merging 188
8.6.4 Complexity of the Algorithm 190
8.7 Deadlock Considerations 190
8.8 Results 190
8.8.1 Experimental Setup 190
8.8.2 Comparison of Results 193
8.9 Conclusions 194
3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks 197
9.1 Introduction 197
9.1.1 3D-Stacking 197
9.1.2 Networks on Chips for 3D ICs 199
9.1.3 Designing NoCs for 3D ICs 201
9.2 3D Architecture and Design Flow 204
9.3 Design Flow Assumptions 205
9.4 Design Approach 206
9.5 Algorithm 208
9.5.1 Phase 1 209
9.5.2 Phase 2 212
9.5.3 Find Paths 213
9.5.4 Switch Position Computation 215
9.6 Experiments and Case Studies 221
9.6.1 Multimedia SoC Case Study 222
9.6.2 Impact of Inter-layer Link Constraint and Comparisons with Mesh 224
9.7 Conclusions 226
3-D NoC on Inductive Wireless Interconnect 228
10.2 Wireless Interconnect with Inductive Coupling 229
10.3 Wireless 3-D NoC for Building Block 3-D ICs 229
10.3.1 Toward Building Block 3-D ICs 231
10.3.1.1 Application Chip Design 232
10.3.1.2 Service Chip Design 232
10.3.2 Wireless 3-D Crossbar Architecture 232
10.3.2.1 Time-Division Multiplex Transfer 232
10.3.2.2 Static TDM Scheme 233
10.3.2.3 Dynamic TDM Scheme 234
10.3.2.4 Hardware Structure 235
10.3.2.5 TX Module Architecture 235
10.3.2.6 RX Module Architecture 236
10.3.2.7 Vertical Crossbar Architecture 236
10.3.2.8 Communication Protocol 237
10.3.2.9 Downstream Transfer 237
10.3.2.10 Upstream Transfer 238
10.4 An Implementation Example: MuCCRA-Cube 239
10.4.1 PE Array Structure in a Die 239
10.4.1.1 PE Structure 240
10.4.2 Homogeneous Stacking 242
10.4.3 3-D Inductive Connection Channels 244
10.4.4 Three-Phase Interleaving Scheme 245
10.4.5 Prototype Chip 246
10.4.6 Communication Link 247
10.4.7 Execution Performance 248
10.5 Research Perspective 249
Influence of Stacked 3D Memory/Cache Architectures on GPUs 252
11.1 Introduction 252
11.2 Background 253
11.2.1 How Do GPUs Work? 253
11.2.2 GPU Hardware Architecture 254
11.2.3 An Example of a Modern GPU: NVIDIA GeForce GTX280 257
11.2.4 3D Technology 258
11.2.5 MRAM 259
11.3 Employing 3D Technology in GPUs 262
11.3.1 Why 3D Technology? 262
11.3.2 Area Estimation Model 263
11.3.3 Cost Model 263
11.3.4 Power Model and Thermal Profiling 265
11.4 Evaluating 3D-Based GPU 265
11.4.1 The Design Space 266
11.4.2 Simulation Environment of GPU Architecture 266
11.4.3 Experiments and Results 267
11.4.4 Iso-Cost Designs 269
11.4.5 Power and Thermal Constraints 271
11.4.6 MRAM as an Alternative to SRAM 272
11.5 Summary 273
Index 275

Erscheint lt. Verlag 8.11.2010
Reihe/Serie Integrated Circuits and Systems
Zusatzinfo X, 278 p.
Verlagsort New York
Sprache englisch
Themenwelt Mathematik / Informatik Informatik Grafik / Design
Mathematik / Informatik Informatik Software Entwicklung
Technik Elektrotechnik / Energietechnik
Schlagworte Embedded Systems • Error Control in Network on Chip • Integrated Circuit Design • Network on Chip • On-Chip Interconnect
ISBN-10 1-4419-7618-3 / 1441976183
ISBN-13 978-1-4419-7618-5 / 9781441976185
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