An Introduction to CAD for VLSI

1. Integrated Circuit Design.- to Integrated Circuit Design.- The Integrated Circuit Design Process.- Variances from This Model of the Design Process.- Managing the Complexity of a Design.- Exercises.- References.- 2. Parsing.- Reading Files.- Describing a Data Format.- An Example.- Parser Overview.- Implementation of the Parser.- Internal Parser Procedures.- The Token Scanner.- Building a Data Structure.- Data Structures.- The Semantics Module.- Memory Usage Issues.- Writing Layout Files.- Exercises.- References.- 3. Graphics.- Output Devices.- Graphical Output Primitives.- Virtual Screen Coordinates.- User Coordinates.- Clipping and Viewports.- Summary of Graphics Output Features.- Summary of Coordinate Systems.- Color.- Graphical Input.- Dynamic Displays.- Exercises.- References.- 4. Plotting Layout.- The Core of a Plotter.- The Command Loop.- Loading a File.- Displaying a Cell.- Necessary Additions.- Desirable Features.- Practical Considerations.- Considerations for Pen Plotters.- Considerations for Raster Plotters.- Exercises.- References.- 5. Layout Editor.- Overview of a Layout Editor.- Turning the Plotter Into an Editor.- Pointing As an Alternative to Typing Positions.- Filters.- Editor State.- Modes and Modeless Editors.- Menus As an Alternative to Typing Commands.- Data Structures.- Essential Features.- Desirable Features.- User Interface.- The Database Alternative To Reading and Writing Files.- Symbolic Layout.- Schematic Editor.- Exercises.- References.- 6. Layout Language.- Embedded Language.- A Simple System.- A More Usable System.- Layout Language Procedures.- Data Structures.- Example.- Symbolic Layout.- The Example Again.- Using Bounding Boxes and Connectors.- Reading Layout Files.- Using Language Facilities.- Parameterized Cells.- The Layout Language Module As a LayoutParser.- A Procedural Netlist Generator.- Drawbacks of a Layout Language.- Exercises.- References.- 7. Layout Generators.- Parameterized Cells.- PLA Generator.- to Silicon Compilation.- Datapath Compiler.- to Placement and Routing.- Exercises.- References.- 8. Layout Analysis.- Overview and Background.- Design Rules.- Object-Based DRC.- Edge-Based Layout Operations.- Handling Intersecting Edges.- Polygon Merging.- Arbitrary Boolean Operations On Layout Layers.- Resizing Layout.- Using Bloat and Shrink to Perform a Design Rule Check.- A More Efficient DRC.- Connectivity.- Performance Optimization Considerations.- Reporting DRC Errors.- Ambiguous Corner Checks.- Glitches.- Technology File.- Fast Sorting For Edge Files.- Circuit Extraction.- Options.- Mask Tooling.- Other Algorithms.- Exercises.- References.- 9. Simulation.- Types of Simulators.- A Simple Behavioral Simulator.- Time and the Event Queue.- Modelling Shared Busses.- A Logic Simulator.- Controlling and Observing the Simulation.- Managing the Event Queue.- Simulating Transistors.- Transistor Simulation Example.- Debugging Commands.- Enhancements to the Transistor Simulation Algorithms.- Static Checks.- Multi-Level Simulation.- High-level Input.- Testing Integrated Circuits.- Fault Simulation.- Exercises.- References.