Processor Description Languages (eBook)

Front Cover 1
Processor Description Languages Applications 4
Copyright Page 5
Table of Contents 8
List of Contributors 18
Preface 26
About the Editors 28
Chapter 1. Introduction to Architecture Description Languages 30
1.1 What is an Architecture Description Language? 31
1.2 ADLs and Other Languages 32
1.3 Classification of Contemporary ADLs 33
1.3.1 Content-based Classification of ADLs 34
1.3.2 Objective-based Classification of ADLs 35
1.4 ADLs: Past, Present, and Future 37
1.5 Book Organization 38
References 39
Chapter 2. ADL-driven Methodologies for Design Automation of Embedded Processors 42
2.1 Design Space Exploration 42
2.2 Retargetable Compiler Generation 43
2.2.1 Retargetability Based on ADL Content 45
2.2.2 Retargetability Based on Compiler Phases 46
2.2.3 Retargetability Based on Architectural Abstractions 47
2.3 Retargetable Simulator Generation 50
2.3.1 Interpretive Simulation 51
2.3.2 Compiled Simulation 51
2.3.3 Mixed Approaches 51
2.4 Architecture Synthesis 52
2.4.1 Implementation Generation Using Processor Templates 52
2.4.2 ADL-driven Implementation Generation 53
2.5 Top-Down Validation 53
2.5.1 Validation of ADL Specification 54
2.5.2 Implementation Validation 56
2.6 Conclusions 59
References 59
Chapter 3. MIMOLA—A Fully Synthesizable Language 64
3.1 Introduction 64
3.1.1 Origin of the Language 64
3.1.2 Purpose of the Language 65
3.1.3 Related Work: State of the Art in the Early Years 67
3.1.4 Outline of This Chapter 68
3.2 Salient Features of the Mimola Language 68
3.2.1 Overall Structure of Description 68
3.2.2 Declarations, Data Types, and Operations 68
3.2.3 Program Definition 69
3.2.4 Structure Definition 72
3.2.5 Linking Behavior and Structure 75
3.2.6 Putting Things Together 77
3.3 Tools and Results 77
3.3.1 Design Flow 77
3.3.2 The Front-end and Internal Design Representations 77
3.3.3 Mapping to Register Transfers 78
3.3.4 Simulation 78
3.3.5 Architectural Synthesis 79
3.3.6 Test Program Generation 83
3.3.7 Code Generation 85
3.3.8 Overall View of the Dependence among MSS Tools 86
3.3.9 Designs Using MSS2 87
3.4 Conclusions 88
3.4.1 Evolution of Ideas and Directions 88
3.4.2 What Went Wrong and What Went Right 88
3.4.3 Summary 89
References 89
Chapter 4. nML: A Structural Processor Modeling Language for Retargetable Compilation and ASIP Design 94
4.1 Introduction 94
4.2 The nML Processor Description Formalism 95
4.3 A Structural Skeleton of the Processor 95
4.3.1 Memories and Registers 96
4.3.2 Storage Aliases 97
4.3.3 Transitory Storage 97
4.3.4 Immediate Constants and Enumeration Types 98
4.3.5 Functional Units 99
4.4 Instruction-Set Grammar 99
4.4.1 Breaking Down the Instruction Set: AND Rules and OR Rules 101
4.4.2 The Grammar Attributes 102
4.4.3 Synthesized Attributes 102
4.4.4 Action Attribute 103
4.4.5 Image Attribute 106
4.4.6 Syntax Attribute 107
4.4.7 Mode Rules and Value Attributes 107
4.4.8 Inherited Attributes 109
4.5 Pipeline Hazards: Stalls and Bypasses 109
4.5.1 Control Hazards 110
4.5.2 Structural and Data Hazards 111
4.6 The Evolution of nML 114
4.7 A Retargetable Tool Suite for ASIPs 116
4.7.1 Chess: A Retargetable C Compiler 116
4.7.2 Checkers: A Retargetable Instruction-set Simulator Generator 117
4.7.3 Go: A Hardware Description Language Generator 117
4.7.4 Risk: A Retargetable Test-program Generator 117
4.7.5 Broad Architectural Scope 117
4.8 Design Examples 119
4.8.1 Portable Audio and Hearing Instruments 119
4.8.2 Wireline Modems 119
4.8.3 Wireless Modems 120
4.8.4 Video Coding 120
4.8.5 Network Processing 120
4.9 Conclusions 121
References 121
Chapter 5. LISA: A Uniform ADL for Embedded Processor Modeling, Implementation, and Software Toolsuite Generation 124
5.1 Language-based ASIP Modeling 125
5.1.1 Intuitive Modeling Idea 125
5.1.2 ISA Modeling 125
5.1.3 Structure Modeling: Base Processor 128
5.1.4 Levels of Abstraction in LISA 129
5.1.5 LISA-based Processor Design 130
5.2 Automatic Software Toolsuite Generation 131
5.2.1 Instruction-set Simulator 132
5.2.2 The Compiler Designer 134
5.2.3 Custom Instruction Synthesis for LISA-based Processor Design 137
5.2.4 Instruction Opcode Synthesis 138
5.3 Automatic Optimized Processor Implementation 139
5.3.1 Automatic Generation of RTL Processor Description 139
5.3.2 Area and Timing-driven Optimizations 140
5.3.3 Energy-driven Optimizations 141
5.3.4 Automatic Generation of JTAG Interface and Debug Mechanism 142
5.4 Processor Verification 142
5.4.1 Equivalence Check via Simulation 143
5.4.2 Generation of Test Vectors from LISA Descriptions for Instruction-set Verification 144
5.5 System-Level Integration 146
5.5.1 Retargetable Processor Integration 147
5.5.2 Multiprocessor Simulation 148
5.6 Compact Modeling of Advanced Architectures 149
5.6.1 VLIW Architecture Modeling 150
5.6.2 Partially Reconfigurable Processor Modeling 151
5.7 Case Study 152
5.7.1 ASIP Development for Retinex-like Image and Video Processing 153
5.7.2 Retargetable Compiler Optimization for SIMD Instructions 156
5.8 Conclusions 159
References 159
Chapter 6. Expression: An ADL for Software Toolkit Generation, Exploration, and Validation of Programmable SOC Architectures 162
6.1 Expression ADL 163
6.1.1 Structure 164
6.1.2 Behavior 166
6.2 Software Toolkit Generation and Exploration 168
6.2.1 Retargetable Compiler Generation 169
6.2.2 Retargetable Simulator Generation 171
6.2.3 Design Space Exploration 173
6.3 Architecture Synthesis for Rapid Prototyping 177
6.3.1 Synthesizable HDL Generation 177
6.3.2 Rapid Prototyping and Exploration 178
6.4 Functional Verification 180
6.4.1 Specification Validation 181
6.4.2 Test Generation Using Model Checking 182
6.4.3 Implementation Validation 185
6.5 Conclusions 187
References 188
Chapter 7. ASIP Meister 192
7.1 Overview of ASIP Meister 192
7.1.1 Framework Overview 193
7.1.2 Features 196
7.1.3 A Short History 197
7.1.4 ASIP Meister Usage in Academia 197
7.2 Architecture Model 197
7.3 ADL in ASIP Meister 199
7.3.1 Overview of ADL Structure 199
7.3.2 Specification Entry Using GUI 200
7.3.3 Microoperation Description 200
7.3.4 VLIW Extension 203
7.4 Generation of HDL Description 205
7.4.1 DFG Construction from Microoperation Description 206
7.4.2 Pipeline Registers and Datapath Selectors Insertion 206
7.5 Case Study 208
7.5.1 MIPS and DLX 208
7.5.2 M32R 209
7.5.3 MeP 209
7.6 Conclusion 210
7.7 Acknowledgments 210
References 211
Chapter 8. TIE: An ADL for Designing Application-specific Instruction Set Extensions 212
8.1 Introduction 212
8.1.1 Adapting the Processor to the Application 212
8.1.2 Tensilica Instruction Extension Language and Compiler 213
8.2 Design Methodology and Tools 213
8.2.1 Designing Application-specific Instructions 213
8.2.2 Design Automation with the TIE Compiler 215
8.3 Basics of Tie Language 216
8.3.1 A basic TIE Acceleration Example 216
8.3.2 Defining a Basic TIE Instruction 217
8.3.3 Instruction Encodings 218
8.3.4 Instruction Datapath 219
8.4 Adding Processor State 221
8.4.1 Defining a State Register 221
8.4.2 Defining a Register File 223
8.4.3 Data Type and Compiler Support 225
8.4.4 Data Parallelism and SIMD 227
8.5 Vliw Machine Design 228
8.5.1 Defining a VLIW Instruction 229
8.5.2 Hardware Cost of VLIW 230
8.6 Language Constructs for Efficient Hardware Implementation 230
8.6.1 Sharing Hardware between Instructions 230
8.6.2 TIE Functions 231
8.6.3 Defining Multicycle Instructions 232
8.7 Custom Data Interfaces 234
8.7.1 Import Wire and Export State 235
8.7.2 TIE Queue 235
8.7.3 TIE Lookup 238
8.8 Hardware Verification 239
8.8.1 Microarchitectural Verification 240
8.9 Case Study of An Audio DSP Design 241
8.9.1 Architecture and ISA Overview 241
8.9.2 Implementation and Performance 242
8.10 Conclusions 243
References 244
Chapter 9. MADL—An ADL Based on a Formal and Flexible Concurrency Model 246
9.1 Introduction 246
9.2 Operation State Machine Model 247
9.2.1 Static OSM Model 248
9.2.2 Dynamic OSM Model 251
9.2.3 Scheduling of the OSM Model 253
9.3 MADL 255
9.3.1 The AND-OR Graph: A Review 256
9.3.2 The Core Layer 257
9.3.3 The Annotation Layer 260
9.4 Support for Tools 262
9.4.1 Cycle Accurate Simulator (CAS) 262
9.4.2 Instruction Set Simulator 264
9.4.3 Disassembler 264
9.4.4 Register Allocator 264
9.4.5 Instruction Scheduler 266
9.5 Results 268
9.6 Related Work 271
9.7 Conclusion 273
References 273
Chapter 10. ADL++: Object-Oriented Specification of Complicated Instruction Sets and Microarchitectures 276
10.1 Flexible Architecture Simulation Toolset (FAST) 277
10.1.1 Overview of the Toolset 277
10.2 The FAST/ADL Model 278
10.2.1 Timing of Events 280
10.2.2 Time Annotated Actions and Parallelism in the Microarchitecture 281
10.2.3 Microarchitecture Specification 282
10.2.4 ISA Specification 286
10.2.5 Putting It Together 288
10.3 Review of Complex Instruction Set Architectures 289
10.3.1 Variable Length Instructions 289
10.3.2 Many Memory Addressing Modes 290
10.3.3 Overlapping Registers 291
10.3.4 Mixed Arguments 292
10.3.5 Assembly Language Syntax 292
10.4 Sets and Regular Expressions as Language Constructs 293
10.4.1 Registers and Their Specification Using Sets 293
10.4.2 Regular Expressions and Addressing Modes 294
10.5 Instruction Templates and Multiple Conditional Inheritance 295
10.5.1 Inheritance with a Twist: Multiple Conditional Inheritance 296
10.5.2 Instruction Template 296
10.6 Object-Oriented Microarchitecture Specification 299
10.6.1 Artifacts as Objects 299
10.6.2 Deriving Complex Architectures From Objects 301
10.7 Epilogue 301
10.8 History of Fast and ADL++ 301
References 302
Chapter 11. Processor Design with ArchC 304
11.1 Overview 304
11.2 Syntax and Semantics 305
11.3 Integration Through a TLM Interface 312
11.3.1 ArchC TLM Interfaces and Protocol 313
11.3.2 TLM Interrupt Port 314
11.3.3 A Word on ArchC Simulators 315
11.4 A Multicore Platform Example 317
11.5 Conclusions 322
References 322
Chapter 12. MAML: An ADL for Designing Single and Multiprocessor Architectures 324
12.1 History of MAML 325
12.2 Description of Single Processor Architectures 327
12.2.1 Syntax 327
12.2.2 Example of a VLIW Processor Architecture 334
12.3 Description of Multiprocessors 335
12.3.1 Related Work 336
12.3.2 Description of Parallel Processing Elements 337
12.3.3 Parametric Domains as a Description Paradigm 339
12.3.4 Description of Adaptive Interconnect Topologies 342
12.3.5 Case Study of a Tightly Coupled Processor Arrays 345
12.4 Approaches and Tools Around MAML 346
12.4.1 Application Mapping 347
12.4.2 Design Framework 348
12.4.3 Interactive Visual Architecture Entry 349
12.4.4 Simulator Generation 350
12.4.5 Architecture Synthesis for Rapid Prototyping 353
12.5 Conclusions and Future Work 353
12.6 Acknowledgments 354
References 354
Chapter 13. GNR: A Formal Language for Specification, Compilation, and Synthesis of Custom Embedded Processors 358
13.1 Introduction 358
13.2 Overview of NISC Technology 361
13.3 Modeling NISC Architectures and Systems 364
13.3.1 GNR Formalism 366
13.3.2 GNR Rules 368
13.3.3 GNR Syntax 370
13.3.4 Basic Components 370
13.3.5 Hierarchical Components 371
13.3.6 Modeling an NISC Architecture 372
13.3.7 Communication Modeling 376
13.3.8 Generating RTL Code from GNR 380
13.4 Experiments: Design-Space Exploration Using NISC and GNR 382
13.4.1 Designing General-purpose NISCs 382
13.4.2 Custom Datapath Design for DCT 386
13.4.3 Communicating NISC Components 392
13.5 Conclusion 394
References 395
13.6 Index Terms 396
Chapter 14. HMDES, ISDL, and Other Contemporary ADLs 398
14.1 HMDES 398
14.1.1 HMDES Language 398
14.1.2 Structural Overview of Machine Description 402
14.1.3 Trimaran Infrastructure 412
14.2 ISDL 413
14.2.1 ISDL Language 414
14.2.2 ISDL-driven Methodologies 417
14.3 RADL 419
14.4 SIM-nML 419
14.5 UDL/I 421
14.6 Flexware 421
14.7 Valen-C 421
14.8 TDL 422
14.9 Conclusions 422
References 423
Index 424