VLSI Physical Design: From Graph Partitioning to Timing Closure - Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu

VLSI Physical Design: From Graph Partitioning to Timing Closure

Buch | Softcover
310 Seiten
2014
Springer (Verlag)
978-94-007-9020-9 (ISBN)
85,59 inkl. MwSt
LSI Physical Design explores how algorthims can be used to create a geometric chip layout can be created from an abstract circuit design. The text emphasizes essential, fundamental techniques, ranging from hypergraph partictioning and circuit placement to timing closure.
Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact.



 



"VLSI Physical Design: From Graph Partitioning to Timing Closure"



introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.

                    
   

Andrew B. Kahng is Professor of CSE and ECE at UC San Diego, where he holds the endowed chair in High-Performance Computing. He has served as visiting scientist at Cadence (1995-1997) and as founder, chairman and CTO at Blaze DFM (2004-2006). Jens Lienig is Professor of Electrical Engineering at TU Dresden. He is also the director of the Institute of Electromechanical and Electronic Design at TUD. He has worked as project manager at Tanner Research, Inc. (1996-1999) and Robert Bosch GmbH (1999-2002). Igor L. Markov is a Professor of Electrical Engineering and Computer Science at the University of Michigan. He has worked at Google (2014-2017) and has been with Facebook since 2018. Jin Hu was a PhD student at the Computer Science and Engineering (CSE) Division at the University of Michigan. Afterwards, she has been with IBM Corp. (2013-2017) and Bloomberg L.P.            

1 Introduction. 2 Netlist and System Partitioning. 3 Chip Planning. 4 Global and Detailed Placement. 5 Global Routing. 6 Detailed Routing. 7 Specialized Routing. 8 Timing Closure. A Solutions to Chapter Exercises. B Example CMOS Cell Layouts.

Erscheint lt. Verlag 15.10.2014
Zusatzinfo XI, 310 p.
Verlagsort Dordrecht
Sprache englisch
Maße 155 x 235 mm
Themenwelt Mathematik / Informatik Informatik Theorie / Studium
Informatik Weitere Themen CAD-Programme
Technik Elektrotechnik / Energietechnik
ISBN-10 94-007-9020-1 / 9400790201
ISBN-13 978-94-007-9020-9 / 9789400790209
Zustand Neuware
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