Failure Modes and Mechanisms in Electronic Packages

P. Singh, Puligandla Viswanadham (Autoren)

Buch | Softcover

370 Seiten

2012 | Softcover reprint of the original 1st ed. 1998
Springer-Verlag New York Inc.
978-1-4613-7763-4 (ISBN)

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Those of us who grew up in the "through-hole" age of electronic packaging are probably more amazed and appreciative than are our children at the incredible growth of electronic performance capability. My son, an electrical engineering student, seems almost to take for granted the innovations that leave me somewhat awestruck at times. Electronic circuit designers delight in packing more punch into less volume, while reminding us that their job has become increasingly challenging. The lay person also has learned from the media that the industry has been working wonders in shrinking the transistor and expanding the power of "the chip. " Much attention is focussed on the silicon and on the marvelous production and entertainment tools we now see in our offices and homes. Between the silicon and the end product lies the less publicized world of circuit-level packaging. We leave it to a cadre of technologists to take the schematics and parts lists and to develop the processes that tum the designers' concepts into physical reality. And while the silicon transistor is shrinking, the engineering challenges of packaging multiple chips and associated components into increasingly dense subsystems are growing. Further, the transistor may have to function without failure through severe industrial or military environments over the lifetime of the product.

1 Introduction.- 1.1 The Technology.- 1.2 Packaging Failure.- 1.3 Approach and Methodology.- 1.4 Packaging Hierarchy.- 1.5 Failure Detection.- 1.6 Analysis.- 1.7 Modes and Mechanisms.- 1.8 Physics of failure and statistical models.- 1.9 Prevention.- 1.10 The Future.- 1.11 Suggested Readings.- 2 Electronics Packaging.- 2.1 Introduction.- 2.2 Packaging Nomenclature.- 2.3 Package Function.- 2.4 Plated-Through-Hole and Surface Mount Technology.- 2.5 Chip Level Packaging.- 2.6 Printed Circuit Board Assembly.- 2.7 Connectors, Cables, and Sockets.- 2.8 Box Level Package.- 2.9 Cost of Failures.- 2.10 Summary.- 2.11 Suggested Readings.- 2.12 References.- 3 Why Failures Occur.- 3.1 Introduction.- 3.2 Stress vs. Strength.- 3.3 Poor Design Practices.- 3.4 Manufacturing Defects.- 3.5 Electrical Design Considerations.- 3.6 Material Characteristics.- 3.7 Summary.- 3.8 References.- 4 Failure Detection.- 4.1 Introduction.- 4.2 Analytical Modeling.- 4.3 Simulation.- 4.4 Environmental Stress Tests.- 4.5 Test Methodology Innovations.- 4.6 Summary.- 4.7 Suggested Readings.- 4.8 References.- 5 Failure Analysis.- 5.1 Introduction.- 5.2 Visual Inspection.- 5.3 Decapsulation.- 5.4 Moiré Interferometry.- 5.5 Dye Penetrants.- 5.6 Metallurgical Analysis.- 5.7 Chemical Analysis.- 5.8 Atomic Absorption Emission Spectroscopies.- 5.9 UV/Visible Spectroscopy.- 5.10 Infrared Spectroscopy.- 5.11 Thermoanalytical Methods.- 5.12 Chromatography.- 5.13 Electron Beam Analysis.- 5.14 Laser Induced Ionization Mass Spectrometry (LIMS).- 5.15 Summary.- 5.16 Suggested Readings.- 5.17 References.- 6 Failure Modes and Mechanisms.- 6.1 Introduction.- 6.2 Failure Mode Types.- 6.3 Printed Circuit Board.- 6.4 Components and Packages.- 6.5 Interconnection Failures.- 6.6 Lead-Free Solders.- 6.7 Corrosion and Migration.-6.8 Connector Failures and Mechanisms.- 6.9 Solder Fatigue and Creep.- 6.10 Failures in Nonsemiconductor Components.- 6.11 Electro Static Discharge (ESD) Failures.- 6.12 PCB Laminates and Hollow Glass Fibers.- 6.13 Radiation-Induced Failures.- 6.14 Summary.- 6.15 Suggested Readings.- 6.16 References.- 7 Failure Models.- 7.1 Introduction.- 7.2 A Survey of Physical Models.- 7.3 Physics-of-Failure Based Models for Devices.- 7.4 Accelerated Factors and Transforms.- 7.5 Summary.- 7.6 References.- 8 Failure Prevention.- 8.1 Introduction.- 8.2 Concurrent Engineering and DFM.- 8.3 DFM Examples.- 8.4 Design for Assembly.- 8.5 Design for Test.- 8.6 Design for Qualification.- 8.7 Design for Reliability.- 8.8 Continuous Improvement Through Defect Management.- 8.9 Summary.- 8.10 References.

Zusatzinfo	XXI, 370 p.
Verlagsort	New York, NY
Sprache	englisch
Maße	155 x 235 mm
Themenwelt	Informatik ► Theorie / Studium ► Algorithmen
	Technik ► Elektrotechnik / Energietechnik
	Technik ► Maschinenbau
ISBN-10	1-4613-7763-3 / 1461377633
ISBN-13	978-1-4613-7763-4 / 9781461377634
Zustand	Neuware