Designing Embedded Processors (eBook)

Dr. Sri Parameswaran received his B.Eng Degree from Monash University and his Ph.D degree from the University of Queensland in Australia. He has held visiting appointments at University of California, Kyushu University and Australian National University. He has also worked as a consultant to the NEC Research laboratories at Princeton, USA and to the Asian Development Bank in Philippines. Currently Dr Parameswaran is at the University of New South Wales and is the Program Director of Computer Engineering. He has served on several program committees such as ICCAD, Euro-DAC, DATE, Codes-ISSS, CASES, APCHDL etc. He has given full day tutorials at ICCAD, Euro DAC and VLSI Design Conference. In 2002, he served as the program committee chair for the IEEE/ACM Codes Hardware/Software Co-design Symposium. Dr Parameswaran’s research interests are in Application Specific Instruction Set Processors and Low power Design for Embedded systems. He leads a group of fifteen researchers, and holds grants from Australian Research Council and Industry. Dr. Joerg Henkel received his Master and Ph.D ("cum laude") degrees both from the Technical University of Braunschweig, Germany. He then joined the Computer & Communication Research Laboratories CCRL (now NEC Laboratories America) in Princeton, NJ, where he led various projects in the areas of low power system level design and advanced embedded architectures. In between, he had an appointment as a visiting professor at the Univ. of Notre Dame, IN. Dr. Henkel is currently with Karlsruhe University (TH), Germany, where he is directing the Chair for Embedded Systems CES. He has served or is serving as a program committee member for major conferences in electronic design automation and embedded system design like ICCAD, DATE, ASP-DAC, ISLPED, Codes-ISSS, CASES, RTSS, RSP. He has given full-day tutorials at conferences like DAC, ICCAD, DATE and others in the area of embedded system design. In 2001 he served as a Program Chair for the IEEE/ACM Codes Hardware/Software Co-design Symposium and was a General of the same convention in 2002. Furthermore, he was a Program Chair for the 2002 IEEE Workshop on Rapid System Prototyping. He has guest-edited special issues on hardware/software co-design in the IEEE Computer Magazine and on rapid system prototyping with Kluwer. Dr. Henkel holds five patents. He is a Senior Member of the IEEE.

Foreword. Part I: Application Specific Embedded Processors. Chapter 1: Application-Specific Embedded Processors; Parameswaran/Henkel/Cheung. Chapter 2: Low-Power Design with NISC Technology; Gorjiara/Reshadi/Gajski. Chapter 3: Synthesis of Instruction Sets for High Performance and Energy Efficient ASIP; Lee/Choi/Dutt. Chapter 4: A Framework for Extensible Processor Based MPSoC Design; Sun et al. Chapter 5: Design and Run Time Code Compression for Embedded Systems; Parameswaran et al. Part II: Embedded Memories. Chapter 6: Power Optimization Strategies Targeting the Memory Subsystem; Panda. Chapter 7: Layer Assignment Techniques for Low Energy Multi-Layered Memory Organizations; Brockmeyer et al. Chapter 8: Memory Bank Locality and its Usage in Reducing Energy Consumption; Kandemir. Part III: Dynamic Voltage and Frequency Scaling. Chapter 9: Fundamentals of Power Aware Scheduling; Hu/Quan. Chapter 10: Static DVFS Scheduling; Quan/Hu. Chapter 11: Dynamic DVFS Scheduling; Pillai/Shin. Chapter 12: Voltage Selection for time-constrained Multi-Processor Systems; Andrei et al. Part IV: Compiler Techniques. Chapter 13: Compilation Techniques for Power, Energy, and Thermal Management; Kremer. Chapter 14: Compiler-Directed Dynamic CPU Frequency and Voltage Scaling; Hsu/Kremer. Chapter 15: Link Idle Period Exploitation for Network Power Management; Li et al. Chapter 16: Remote Task Mapping. Part V: Multi-Processors. Chapter 17: A Power and Energy Perspective on Multi-Processors; Martin. Chapter 18: System-level Design of Network on Chip Architectures; Chata/Srinivasan. Chapter 19: Power-Performance Modeling and Design for Heterogeneous Multiprocessors; Paul/Meyer. Part VI: Reconfigurable Computing. Chapter 20: Basic of Reconfigurable Computing; Hartenstein. Chapter 21: Dynamic Reconfiguration; Becker/Huebner. Chapter 22: Applications, Design Tools and Low Power Issues in FPGA Reconfiguration; Donlin. Acknowledgments. References. Index.