Low Power Methodology Manual (eBook)

ABOUT THE AUTHORS: Michael Keating is a Synopsys Fellow in the company’s Advanced Technology Group, focusing on IP development methodology, hardware and software design quality and low power design. David Flynn is an ARM R&D Fellow and has been with the company since 1991, specializing in low power System-on-Chip IP deployment and methodology. Robert Aitken is an ARM R&D Fellow. His areas of responsibility include memory architecture, design for testability and design for manufacturability. Alan Gibbons is a Principal Engineer at Synopsys, with a focus on development of advanced methodology and technology for ARM processor-based system design. Kaijian Shi is a Principal Consultant in the Professional Services Group of Synopsys, specializing in low power design methodology and implementation.

Preface 6
Table of Contents 8
1 Introduction 15
1.1 Overview 15
1.2 Scope of the Problem 16
1.3 Power vs. Energy 17
1.4 Dynamic Power 18
1.5 The Conflict Between Dynamic and Static Power 21
1.6 Static Power 22
1.7 Purpose of This Book 24
2 Standard Low Power Methods 27
2.1 Clock Gating 27
2.2 Gate Level Power Optimization 29
2.3 Multi VDD 30
2.4 Multi-Threshold Logic 31
2.5 Summary of the Impact of Standard Low Power Techniques 33
3 Multi- Voltage Design 34
3.1 Challenges in Multi-Voltage Designs 35
3.2 Voltage Scaling Interfaces – Level Shifters 35
3.3 Timing Issues in Multi-Voltage Designs 42
3.4 Power Planning for Multi-Voltage Design 43
3.5 System Design Issues with Multi-Voltage Designs 44
4 Power Gating Overview 45
4.1 Dynamic and Leakage Power Profiles 45
4.2 Impact of Power Gating on Classes of Sub-Systems 48
4.3 Principles of Power Gating Design 49
5 Designing Power Gating 53
5.1 Switching Fabric Design 54
5.2 Signal Isolation 57
5.3 State Retention and Restoration Methods 62
5.4 Power Gating Control 71
5.5 Power Gating Design Verification – RTL Simulation 75
5.6 Design For Test Considerations 82
6.1 Hierarchy and Power Gating 86
6 Architectural Issues for Power Gating 86
6.2 Power Networks and Their Control 89
6.3 Power State Tables and Always On Regions 93
7 A Power Gating Example 95
7.1 Leakage Modes Supported 95
7.2 Design Partitioning 98
7.3 Isolation 102
7.4 Retention 104
7.5 Inferring Power Gating and Retention 105
7.6 Measurements and Analysis 106
8 IP Design for Low Power 111
8.1 Architecture and Partitioning for Power Gating 112
8.2 Power Controller Design for the USB OTG 115
8.3 Issues in Designing Portable Power Controllers 118
8.4 Clocks and Resets 119
8.5 Verification 119
8.6 Packaging IP for Reuse with Power Intent 120
8.7 UPF for the USB OTG Core 121
8.8 USB OTG Power Gating Controller State Machine 124
9 Frequency and Voltage Scaling Design 130
9.1 Dynamic Power and Energy 131
9.2 Voltage Scaling Approaches 134
9.3 Dynamic Voltage and Frequency Scaling (DVFS) 134
9.4 CPU Subsystem Design Issues 138
9.5 Adaptive Voltage Scaling (AVS) 139
9.6 Level Shifters and Isolation 140
9.7 Voltage Scaling Interfaces – Effect on Synchronous Timing 141
9.8 Control of Voltage Scaling 145
10 Examples of Voltage Design and Frequency Scaling Examples of Voltage 147
10.1 Voltage Scaling - A Worked Example for UMC 130nm 147
10.2 65nm Voltage Scaling – A Worked Example for TSMC 158
11 Implementing Multi- Voltage, Power Gated Designs 163
11.1 Design Partitioning 166
11.2 Design Flow Overview 168
11.3 Synthesis 170
11.4 Multi Corner Multi Mode Optimization with Voltage Scaling Designs 179
11.5 Design Planning 181
11.6 Power Planning 185
11.7 Clock Tree Synthesis 188
11.8 Power Analysis 191
11.9 Timing Analysis 192
11.10Low Power Validation 193
11.11 Manufacturing Test 193
12 Physical Libraries 195
12.1 Standard Cell Libraries 195
12.2 Special Cells - Isolation Cells 198
12.3 Special Cells - Level Shifters 203
12.4 Memories 206
12.5 Power Gating Strategies and Structures 208
12.6 Power Gating Cells 212
12.7 Power Gated Standard Cell Libraries 214
13 Retention Register Design 216
13.1 Retention Registers 216
13.2 Memory Retention Methods 226
14 Design of the Power Switching Network 231
14.1 Ring vs. Grid Style 231
14.2 Header vs. Footer Switch 238
14.3 Rail vs. Strap VDD Supply 242
14.4 A Sleep Transistor Example 245
14.5 Wakeup Current and Latency Control Methods 246
14.6 An Example of a Dual Daisy Chain Sleep Transistor Implementation 252
A Sleep Transistor Design 254
A.1 Sleep Transistor Design Metrics 255
PMOS Vth (Vdd=1, T=30, Vbb=0..1V) 260
Vth ( V) 260
A.2 Layout Design for Area Efficiency 265
A.3 Single Row vs. Double Row 267
A.4 In-rush Current and Latency Analysis 268
B UPF Command Syntax 271
B.1 add_pst_state 272
B.2 connect_supply_net 273
B.3 create_power_domain 275
B.4 create_power_switch 277
B.5 create_pst 279
B.6 create_supply_net 280
B.7 create_supply_port 281
B.8 set_domain_supply_net 282
B.9 set_isolation 283
B.10 set_isolation_control 285
B.11 set_level_shifter 287
B.12 set_retention 289
B.13 set_retention_control 291
B.14 set_scope 292
Glossary 294
Bibliography 296
Index 300